IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Volume E100.A , Issue 7
Showing 1-35 articles out of 35 articles from the selected issue
Special Section on Design Methodologies for System on a Chip
• Makoto Ikeda
2017 Volume E100.A Issue 7 Pages 1362
Published: July 01, 2017
Released: July 01, 2017
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• Hiroshi SAITO, Masashi IMAI, Tomohiro YONEDA
Type: PAPER
2017 Volume E100.A Issue 7 Pages 1363-1373
Published: July 01, 2017
Released: July 01, 2017
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• Moon Gi SEOK, Tag Gon KIM, Daejin PARK
Type: PAPER
2017 Volume E100.A Issue 7 Pages 1374-1383
Published: July 01, 2017
Released: July 01, 2017
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The rapid prototyping of a mixed-signal system-on-chip (SoC) has been enabled by reusing predesigned intellectual properties (IPs) and by integrating newly designed IP into the top design of SoC. The IPs have been designed on various hardware description levels, which leads to challenges in simulations that evaluate the prototyping. One traditional solution is to convert these heterogeneous IP models into equivalent models, that are described in a single description language. This conversion approach often requires manual rewriting of existing IPs, and this results in description loss during the model projection due to the absence of automatic conversion tools. The other solutions are co-simulation/emulation approaches that are based on the coupling of multiple simulators/emulators through connection modules. The conventional methods do not have formal theoretical backgrounds and an explicit interface for integrating the simulator into their solutions. In this paper, we propose a general co-simulation approach based on the high-level architecture (HLA) and a newly-defined programming language interface for interoperation (PLI-I) between heterogeneous IPs as a formal simulator interface. Based on the proposed PLI-I and HLA, we introduce formal procedures of integration and interoperation. To reduce integration costs, we split these procedures into two parts: a reusable common library and an additional model-dependent signal-to-event (SE) converter to handle differently abstracted in/out signals between the coupled IPs. During the interoperation, to resolve the different time-advance mechanisms and increase computation concurrency between digital and analog simulators, the proposed co-simulation approach performs an advanced HLA-based synchronization using the pre-simulation concepts. The case study shows the validation of interoperation behaviors between the heterogeneous IPs in mixed-signal SoC design, the reduced design effort in integrating, and the synchronization speedup using the proposed approach.

• Shanlin XIAO, Tsuyoshi ISSHIKI, Dongju LI, Hiroaki KUNIEDA
Type: PAPER
2017 Volume E100.A Issue 7 Pages 1384-1395
Published: July 01, 2017
Released: July 01, 2017
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Object detection is at the heart of nearly all the computer vision systems. Standard off-the-shelf embedded processors are hard to meet the trade-offs among performance, power consumption and flexibility required by object detection applications. Therefore, this paper presents an Application Specific Instruction set Processor (ASIP) for object detection using AdaBoost-based learning algorithm with Haar-like features as weak classifiers. Algorithm optimizations are employed to reduce memory bandwidth requirements without losing reliability. In the proposed ASIP, Single Instruction Multiple Data (SIMD) architecture is adopted for fully exploiting data-level parallelism inherent to the target algorithm. With adding pipeline stages, application-specific hardware components and custom instructions, the AdaBoost algorithm is accelerated by a factor of 13.7x compared to the optimized pure software implementation. Compared with ARM946 and TMS320C64+, our ASIP shows 32x and 7x better throughput, 10x and 224x better area efficiency, 6.8x and 18.8x better power efficiency, respectively. Furthermore, compared to hard-wired designs, evaluation results show an advantage of the proposed architecture in terms of chip area efficiency while maintain a reliable performance and achieve real-time object detection at 32fps on VGA video.

• Rei UENO, Naofumi HOMMA, Takafumi AOKI, Sumio MORIOKA
Type: PAPER
2017 Volume E100.A Issue 7 Pages 1396-1408
Published: July 01, 2017
Released: July 01, 2017
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This paper presents an automatic hierarchical formal verification method for arithmetic circuits over Galois fields (GFs) which are dedicated digital circuits for GF arithmetic operations used in cryptographic processors. The proposed verification method is based on a combination of a word-level computer algebra procedure with a bit-level PPRM (Positive Polarity Reed-Muller) expansion procedure. While the application of the proposed verification method is not limited to cryptographic processors, these processors are our important targets because complicated implementation techniques, such as field conversions, are frequently used for side-channel resistant, compact and low power design. In the proposed method, the correctness of entire datapath is verified over GF(2m) level, or word-level. A datapath implementation is represented hierarchically as a set of components' functional descriptions over GF(2m) and their wiring connections. We verify that the implementation satisfies a given total-functional specification over GF(2m), by using an automatic algebraic method based on the Gröbner basis and a polynomial reduction. Then, in order to verify whether each component circuit is correctly implemented by combination of GF(2) operations, i.e. logic gates in bit-level, we use our fast PPRM expansion procedure which is customized for handling large-scale Boolean expressions with many variables. We have applied the proposed method to a complicated AES (Advanced Encryption Standard) circuit with a masking countermeasure against side-channel attack. The results show that the proposed method can verify such practical circuit automatically within 4 minutes, while any single conventional verification methods fail within a day or even more.

• Theint Theint THU, Jimpei HAMAMURA, Rie SOEJIMA, Yuichiro SHIBATA, Kiy ...
Type: PAPER
2017 Volume E100.A Issue 7 Pages 1409-1417
Published: July 01, 2017
Released: July 01, 2017
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Field Programmable Gate Array (FPGA) based robust model fitting enjoys immense popularity in image processing because of its high efficiency. This paper focuses on the tradeoff analysis of real-time FPGA implementation of robust circle and ellipse estimations based on the random sample consensus (RANSAC) algorithm, which estimates parameters of a statistical model from a data set of feature points which contains outliers. In particular, this paper mainly highlights implementation alternatives for solvers of simultaneous equations and compares Gauss-Jordan elimination and Cramer's rule by changing matrix size and arithmetic processes. Experimental evaluation shows a Cramer's rule approach coupled with long integer arithmetic can reduce most hardware resources without unacceptable degradation of estimation accuracy compared to floating point versions.

• Toshiki HIGASHI, Hiroyuki OCHI
Type: PAPER
2017 Volume E100.A Issue 7 Pages 1418-1426
Published: July 01, 2017
Released: July 01, 2017
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This paper proposes 0-1-A-Ā LUT, a new programmable logic using atom switches, and a delay-optimal mapping algorithm for it. Atom switch is a non-volatile memory device of very small geometry which is fabricated between metal layers of a VLSI, and it can be used as a switch device of very small on-resistance and parasitic capacitance. While considerable area reduction of Look Up Tables (LUTs) used in conventional Field Programmable Gate Arrays (FPGAs) has been achieved by simply replacing each SRAM element with a memory element using a pair of atom switches, our 0-1-A-Ā LUT achieves further area and delay reduction. Unlike the conventional atom-switch-based LUT in which all k input signals are fed to a MUX, one of input signals is fed to the switch array, resulting area reduction due to the reduced number of inputs of the MUX from 2k to 2k-1, as well as delay reduction due to reduced fanout load of the input buffers. Since the fanout of this input buffers depends on the mapped logic function, this paper also proposes technology mapping algorithms to select logic function of fewer number of fanouts of input buffers to achieve further delay reduction. From our experiments, the circuit delay using our k-LUT is 0.94% smaller in the best case compared with using the conventional atom-switch-based k-LUT.

• Kento HASEGAWA, Masao YANAGISAWA, Nozomu TOGAWA
Type: PAPER
2017 Volume E100.A Issue 7 Pages 1427-1438
Published: July 01, 2017
Released: July 01, 2017
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Due to the increase of outsourcing by IC vendors, we face a serious risk that malicious third-party vendors insert hardware Trojans very easily into their IC products. However, detecting hardware Trojans is very difficult because today's ICs are huge and complex. In this paper, we propose a hardware-Trojan classification method for gate-level netlists to identify hardware-Trojan infected nets (or Trojan nets) using a support vector machine (SVM) or a neural network (NN). At first, we extract the five hardware-Trojan features from each net in a netlist. These feature values are complicated so that we cannot give the simple and fixed threshold values to them. Hence we secondly represent them to be a five-dimensional vector and learn them by using SVM or NN. Finally, we can successfully classify all the nets in an unknown netlist into Trojan ones and normal ones based on the learned classifiers. We have applied our machine-learning-based hardware-Trojan classification method to Trust-HUB benchmarks. The results demonstrate that our method increases the true positive rate compared to the existing state-of-the-art results in most of the cases. In some cases, our method can achieve the true positive rate of 100%, which shows that all the Trojan nets in an unknown netlist are completely detected by our method.

• Koki IGAWA, Masao YANAGISAWA, Nozomu TOGAWA
Type: PAPER
2017 Volume E100.A Issue 7 Pages 1439-1451
Published: July 01, 2017
Released: July 01, 2017
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In this paper, we propose a floorplan aware high-level synthesis algorithm with body biasing for delay variation compensation, which minimizes the average leakage energy of manufactured chips. In order to realize floorplan-aware high-level synthesis, we utilize huddle-based distributed register architecture (HDR architecture). HDR architecture divides the chip area into small partitions called a huddle and we can control a body bias voltage for every huddle. During high-level synthesis, we iteratively obtain expected leakage energy for every huddle when applying a body bias voltage. A huddle with smaller expected leakage energy contributes to reducing expected leakage energy of the entire circuit more but can increase the latency. We assign control-data flow graph (CDFG) nodes in non-critical paths to the huddles with larger expected leakage energy and those in critical paths to the huddles with smaller expected leakage energy. We expect to minimize the entire leakage energy in a manufactured chip without increasing its latency. Experimental results show that our algorithm reduces the average leakage energy by up to 39.7% without latency and yield degradation compared with typical-case design with body biasing.

• Yutaka MASUDA, Takao ONOYE, Masanori HASHIMOTO
Type: PAPER
2017 Volume E100.A Issue 7 Pages 1452-1463
Published: July 01, 2017
Released: July 01, 2017
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Software-based error detection techniques, which includes error detection mechanism (EDM) transformation, are used for error localization in post-silicon validation. This paper evaluates the performance of EDM for timing error localization with a noise-aware logic simulator and 65-nm test chips assuming the following two EDM usage scenarios; (1) localizing a timing error occurred in the original program, and (2) localizing as many potential timing errors as possible. Simulation results show that the EDM transformation customized for quick error detection cannot locate electrical timing errors in the original program in the first scenario, but it detects 86% of non-masked errors potential bugs in the second scenario, which mean the EDM performance of detecting electrical timing errors affecting execution results is high. Hardware measurement results show that the EDM detects 25% of original timing errors and 56% of non-masked errors. Here, these hardware measurement results are not consistent with the simulation results. To investigate the reason, we focus on the following two differences between hardware and simulation; (1) design of power distribution network, and (2) definition of timing error occurrence frequency. We update the simulation setup for filling the difference and re-execute the simulation. We confirm that the simulation and the chip measurement results are consistent.

• Shumpei MORITA, Song BIAN, Michihiro SHINTANI, Masayuki HIROMOTO, Taka ...
Type: PAPER
2017 Volume E100.A Issue 7 Pages 1464-1472
Published: July 01, 2017
Released: July 01, 2017
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Replacement of highly stressed logic gates with internal node control (INC) logics is known to be an effective way to alleviate timing degradation due to NBTI. We propose a path clustering approach to accelerate finding effective replacement gates. Upon the observation that there exist paths that always become timing critical after aging, critical path candidates are clustered to select representative path in each cluster. With efficient data structure to further reduce timing calculation, INC logic optimization has first became tractable in practical time. Through the experiments using a processor, 171x speedup has been demonstrated while retaining almost the same level of mitigation gain.

• Takeshi IHARA, Toshiyuki HONGO, Atsushi TAKAHASHI, Chikaaki KODAMA
Type: PAPER
2017 Volume E100.A Issue 7 Pages 1473-1480
Published: July 01, 2017
Released: July 01, 2017
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Self-Aligned Quadruple Patterning (SAQP) is an important manufacturing technique for sub 14nm technology node. Although various routing algorithms for SAQP have been proposed, it is not easy to find a dense SAQP compliant routing pattern efficiently. Even though a grid for SAQP compliant routing pattern was proposed, it is not easy to find a valid routing pattern on the grid. The routing pattern of SAQP on the grid consists of three types of routing. Among them, third type has turn prohibition constraint on the grid. Typical routing algorithms often fail to find a valid routing for third type. In this paper, a simple directed grid-graph for third type is proposed. Valid SAQP compliant two dimensional routing patterns are found effectively by utilizing the proposed directed grid-graph. Experiments show that SAQP compliant routing patterns are found efficiently by our proposed method.

• Yosuke KAKIUCHI, Kiyoharu HAMAGUCHI
Type: PAPER
2017 Volume E100.A Issue 7 Pages 1481-1487
Published: July 01, 2017
Released: July 01, 2017
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Verification of logic designs has been a long-standing bottleneck in the process of hardware design, where its automation and improvement of efficiency has demanding needs. Mainly simulation-based verification has been used for this purpose, and recently, coverage-driven verification has been widely used, of which target is improvement of some metric called coverage. Our target is the metric called toggle coverage. To find input patterns which cause some toggles on each signal, a SAT solver could be used, but this is computationally costly. In this paper, we study the effect of combination of random simulation and usage of a SAT solver. In particular, we use a SAT solver which can find multiple “diverse” solutions. With this solver, we can avoid generating similar patterns, which are unlikely to improve coverage. The experimental results show that, a small number of calls of a SAT solver can improve entire toggle coverage effectively, compared with simple random simulation.

• Masayuki ARAI, Kazuhiko IWASAKI
Type: PAPER
2017 Volume E100.A Issue 7 Pages 1488-1495
Published: July 01, 2017
Released: July 01, 2017
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Shrinking feature sizes and higher levels of integration in semiconductor device manufacturing technologies are increasingly causing the gap between defect levels estimated in the design stage and reported ones for fabricated devices. In this paper, we propose a unified weighted fault coverage approach that includes both bridge and open faults, considering the critical area as the incident rate of each fault. We then propose a test pattern reordering scheme that incorporates our weighted fault coverage with an aim to reduce test costs. Here we apply a greedy algorithm to reorder test patterns generated by the bridge and stuck-at automatic test pattern generator (ATPG), evaluating the relationship between the number of patterns and the weighted fault coverage. Experimental results show that by applying this reordering scheme, the number of test patterns was reduced, on average, by approximately 50%. Our results also indicate that relaxing coverage constraints can drastically reduce test pattern set sizes to a level comparable to traditional 100% coverage stuck-at pattern sets, while targeting the majority of bridge faults and keeping the defect level to no more than 10 defective parts per milion (DPPM) with a 99% manufacturing yield.

• Takahiro YAMAMOTO, Ittetsu TANIGUCHI, Hiroyuki TOMIYAMA, Shigeru YAMAS ...
Type: LETTER
2017 Volume E100.A Issue 7 Pages 1496-1499
Published: July 01, 2017
Released: July 01, 2017
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Approximate computing is considered as a promising approach to design of power- or area-efficient digital circuits. This paper proposes a systematic methodology for design and worst-case accuracy analysis of approximate array multipliers. Our methodology systematically designs a series of approximate array multipliers with different area, delay, power and accuracy characteristics so that an LSI designer can select the one which best fits to the requirements of her/his applications. Our experiments explore the trade-offs among area, delay, power and accuracy of the approximate multipliers.

• Yining XU, Ittetsu TANIGUCHI, Hiroyuki TOMIYAMA
Type: LETTER
2017 Volume E100.A Issue 7 Pages 1500-1502
Published: July 01, 2017
Released: July 01, 2017
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Task mapping is one of the most important design processes in embedded manycore systems. This paper proposes a static task mapping technique for manycore real-time systems. The technique minimizes the number of cores while satisfying deadline constraints of individual tasks.

• Kana SHIMADA, Shogo KITANO, Ittetsu TANIGUCHI, Hiroyuki TOMIYAMA
Type: LETTER
2017 Volume E100.A Issue 7 Pages 1503-1505
Published: July 01, 2017
Released: July 01, 2017
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Task scheduling is one of the most important processes in the design of multicore computing systems. This paper presents a technique for scheduling of malleable tasks. Our scheduling technique decides not only the execution order of the tasks but also the number of cores assigned to the individual tasks, simultaneously. We formulate the scheduling problem as an integer linear programming (ILP) problem, and the optimal schedule can be obtained by solving the ILP problem. Experiments using a standard task-set suite clarify the strength of this work.

• Junghoon OH, Mineo KANEKO
Type: LETTER
2017 Volume E100.A Issue 7 Pages 1506-1510
Published: July 01, 2017
Released: July 01, 2017
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This letter proposes a heuristic algorithm to select check variables, which are points of comparison for error detection, for soft-error tolerant datapaths. Our soft-error tolerance scheme is based on check-and-retry computation and an efficient resource management named speculative resource sharing (SRS). Starting with the smallest set of check variables, the proposed algorithm repeats to add new check variable one by one incrementally and find the minimum latency solution among the series of generated solutions. During the process, each new check variable is selected so that the opportunity of SRS is enlarged. Experimental results show that improvements in latency are achieved compared with the choice of the smallest set of check variables.

• Yusuke HIBINO, Hirofumi IKEO, Nagisa ISHIURA
Type: LETTER
2017 Volume E100.A Issue 7 Pages 1511-1512
Published: July 01, 2017
Released: July 01, 2017
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This letter presents a test suite CF3 designed to find bugs in arithmetic optimizers of C compilers. It consists of 13,720 test programs containing all the expression patterns covering all the permutations of 3 operators from 14 operators. CF3 detected more than 70 errors in GCC 4.2-4.5 within 2 hours.

Regular Section
• Ryosuke KUNII, Takashi YOSHIDA, Naoyuki AIKAWA
Type: PAPER
Subject area: Digital Signal Processing
2017 Volume E100.A Issue 7 Pages 1513-1521
Published: July 01, 2017
Released: July 01, 2017
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Linear phase maximally flat digital differentiators (DDs) with stopbands obtained by minimizing the Lp norm are filters with important practical applications, as they can differentiate input signals without distortion. Stopbands designed by minimizing the Lp norm can be used to control the relationship between the steepness in the transition band and the ripple scale. However, linear phase DDs are unsuitable for real-time processing because each group delay is half of the filter order. In this paper, we proposed a design method for a low-delay maximally flat low-pass/band-pass FIR DDs with stopbands obtained by minimizing the Lp norm. The proposed DDs have low-delay characteristics that approximate the linear phase characteristics only in the passband. The proposed transfer function is composed of two functions, one with flat characteristics in the passband and one that ensures the transfer function has Lp approximated characteristics in the stopband. In the optimization of the latter function, Newton's method is employed.

• Tri Quoc TRUONG, Tadashi TSUBONE, Kuniyasu SHIMIZU, Naohiko INABA
Type: PAPER
Subject area: Nonlinear Problems
2017 Volume E100.A Issue 7 Pages 1522-1531
Published: July 01, 2017
Released: July 01, 2017
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This report presents experimental measurements of mixed-mode oscillations (MMOs) generated by a weakly driven four-segment piecewise linear Bonhoeffer-van der Pol (BVP) oscillator. Such a roughly approximated simple piecewise linear circuit can generate MMOs and mixed-mode oscillation-incrementing bifurcations (MMOIBs). The laboratory experiments well agree with numerical results. We experimentally and numerically observe time series and Lorenz plots of MMOs generated by successive and nonsuccessive MMOIBs.

• Haruka MIZUTA, Takehiro ITO, Xiao ZHOU
Type: PAPER
Subject area: Algorithms and Data Structures
2017 Volume E100.A Issue 7 Pages 1532-1540
Published: July 01, 2017
Released: July 01, 2017
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We study a reconfiguration problem for Steiner trees in an unweighted graph, which determines whether there exists a sequence of Steiner trees that transforms a given Steiner tree into another one by exchanging a single edge at a time. In this paper, we show that the problem is PSPACE-complete even for split graphs, while solvable in linear time for interval graphs and for cographs.

• Guoliang LI, Lining XING, Zhongshan ZHANG, Yingwu CHEN
Type: PAPER
Subject area: Graphs and Networks
2017 Volume E100.A Issue 7 Pages 1541-1551
Published: July 01, 2017
Released: July 01, 2017
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Bayesian networks are a powerful approach for representation and reasoning under conditions of uncertainty. Of the many good algorithms for learning Bayesian networks from data, the bio-inspired search algorithm is one of the most effective. In this paper, we propose a hybrid mutual information-modified binary particle swarm optimization (MI-MBPSO) algorithm. This technique first constructs a network based on MI to improve the quality of the initial population, and then uses the decomposability of the scoring function to modify the BPSO algorithm. Experimental results show that, the proposed hybrid algorithm outperforms various other state-of-the-art structure learning algorithms.

• Zhaoyang GUO, Bo WANG, Xin'an WANG
Type: LETTER
Subject area: Speech and Hearing
2017 Volume E100.A Issue 7 Pages 1552-1556
Published: July 01, 2017
Released: July 01, 2017
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A comprehensive method applying a nonlinear frequency compression (FC) as complementary to multi-band loudness compensation is proposed, which is able to improve loudness compensation and simultaneously increase high-frequency speech intelligibility for digital hearing aids. The proposed nonlinear FC (NLFC) improves the conventional methods in the aspect that the compression ratio (CR) is adjusted based on the speech intelligibility percentage in different frequency ranges. Then, an adaptive wide dynamic range compression (AWDRC) with a time-varying CR is applied to achieve adaptive loudness compensation. The experimental test results show that the mean speech identification is improved in comparison with the state-of-art methods.

• Shunsuke KOSHITA, Hiroyuki MUNAKATA, Masahide ABE, Masayuki KAWAMATA
Type: LETTER
Subject area: Digital Signal Processing
2017 Volume E100.A Issue 7 Pages 1557-1561
Published: July 01, 2017
Released: July 01, 2017
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In the field of adaptive notch filtering, Monotonically Increasing Gradient (MIG) algorithm has recently been proposed by Sugiura and Shimamura [1], where it is claimed that the MIG algorithm shows monotonically increasing gradient characteristics. However, our analysis has found that the underlying theory in [1] includes crucial errors. This letter shows that the formulation of the gradient characteristics in [1] is incorrect, and reveals that the MIG algorithm fails to realize monotonically increasing gradient characteristics when the input signal includes white noise.

• Jiangbo LIU, Guan GUI, Wei XIE, Xunchao CONG, Qun WAN, Fumiyuki ADACHI
Type: LETTER
Subject area: Digital Signal Processing
2017 Volume E100.A Issue 7 Pages 1562-1566
Published: July 01, 2017
Released: July 01, 2017
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Based on the reconstruction of the augmented interference-plus-noise (IPN) covariance matrix (CM) and the estimation of the desired signal's extended steering vector (SV), we propose a novel robust widely linear (WL) beamforming algorithm. Firstly, an extension of the iterative adaptive approach (IAA) algorithm is employed to acquire the spatial spectrum. Secondly, the IAA spatial spectrum is adopted to reconstruct the augmented signal-plus-noise (SPN) CM and the augmented IPNCM. Thirdly, the extended SV of the desired signal is estimated by using the iterative robust Capon beamformer with adaptive uncertainty level (AU-IRCB). Compared with several representative robust WL beamforming algorithms, simulation results are provided to confirm that the proposed method can achieve a better performance and has a much lower complexity.

• Zhong-Jian KANG, Yi-Jia ZHANG, Xin-Ling GUO, Zhe-Ming LU
Type: LETTER
Subject area: Systems and Control
2017 Volume E100.A Issue 7 Pages 1567-1570
Published: July 01, 2017
Released: July 01, 2017
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The application of complex network theory to power grid analysis has been a hot topic in recent years, which mainly manifests itself in four aspects. The first aspect is to model power system networks. The second aspect is to reveal the topology of the grid itself. The third aspect is to reveal the inherent vulnerability and weakness of the power network itself and put forward the pertinent improvement measures to provide guidance for the construction of power grid. The last aspect is to analyze the mechanism of cascading failure and establish the cascading fault model of large power failure. In the past ten years, by using the complex network theory, many researchers have investigated the structural vulnerability of power grids from the point of view of topology. This letter studies the structural vulnerability of power grids according to the effect of selective node removal. We apply several kinds of node centralities including recently-presented second-order centrality (SOC) to guide the node removal attack. We test the effectiveness of all these centralities in guiding the node removal based on several IEEE power grids. Simulation results show that, compared with other node centralities, the SOC is relatively effective in guiding the node removal and can destroy the power grid with negative degree-degree correlation in less steps.

• Shiu MOCHIYAMA, Ryo TAKAHASHI, Takashi HIKIHARA
Type: LETTER
Subject area: Systems and Control
2017 Volume E100.A Issue 7 Pages 1571-1574
Published: July 01, 2017
Released: July 01, 2017
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The power packet dispatching system, in which electric power is transferred in a pulse-shaped form with information, is expected to realize dynamical management of multiple power sources in independent systems such as robots. In this letter, close-loop control of a stepper motor by power packets is discussed. The precise angle control is achieved by the combined transfer of power and control information in experiments.

• Masaki KOBAYASHI
Type: LETTER
Subject area: Nonlinear Problems
2017 Volume E100.A Issue 7 Pages 1575-1577
Published: July 01, 2017
Released: July 01, 2017
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Quaternionic neural networks are extensions of neural networks using quaternion algebra. 3-D and 4-D quaternionic MLPs have been studied. 3-D quaternionic neural networks are useful for handling 3-D objects, such as Euclidean transformation. As for Hopfield neural networks, only 4-D quaternionic Hopfield neural networks (QHNNs) have been studied. In this work, we propose the 3-D QHNNs. Moreover, we define the energy, and prove that it converges.

• Haibo DAI, Chunguo LI, Luxi YANG
Type: LETTER
Subject area: Numerical Analysis and Optimization
2017 Volume E100.A Issue 7 Pages 1578-1582
Published: July 01, 2017
Released: July 01, 2017
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In this letter, we propose two robust and distributed game-based algorithms, which are the modifications of two algorithms proposed in [1], to solve the joint base station selection and resource allocation problem with imperfect information in heterogeneous cellular networks (HCNs). In particular, we repeatedly sample the received payoffs in the exploitation stage of each algorithm to guarantee the convergence when the payoffs of some users (UEs) in [1] cannot accurately be acquired for some reasons. Then, we derive the rational sampling number and prove the convergence of the modified algorithms. Finally, simulation results demonstrate that two modified algorithms achieve good convergence performances and robustness in the incomplete information scheme.

• Tao LIU, Chengqian XU, Yubo LI
Type: LETTER
Subject area: Information Theory
2017 Volume E100.A Issue 7 Pages 1583-1587
Published: July 01, 2017
Released: July 01, 2017
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This letter proposes a class of polyphase zero correlation zone (ZCZ) sequence sets with low inter-set cross-correlation property. The proposed ZCZ sequence sets are constructed from DFT matrices and r-coincidence sequences. Each ZCZ sequence set is optimal, and the absolute value of the cross-correlation function of sequences from different sets is less than or equal to $r\sqrt{N}$, where N denotes the length of each sequence. These ZCZ sequence sets are suitable for multiuser environments.

• Yi RAO, Ruihu LI
Type: LETTER
Subject area: Coding Theory
2017 Volume E100.A Issue 7 Pages 1588-1591
Published: July 01, 2017
Released: July 01, 2017
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Locally repairable codes have recently been applied in distributed storage systems because of their excellent local erasure-correction capability. A locally repairable code is a code with locality r, where each code symbol can be recovered by accessing at most r other code symbols. In this paper, we study the existence and construction of binary cyclic codes with locality 2. An overview of best binary cyclic LRCs with length 7≤n≤87 and locality 2 are summarized here.

• Guojie HU, Kui XU, Youyun XU
Type: LETTER
Subject area: Coding Theory
2017 Volume E100.A Issue 7 Pages 1592-1595
Published: July 01, 2017
Released: July 01, 2017
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In this letter, we focus on a system where N sources send nN different packets to one destination, through MN relays. Each relay employs random linear network coding to encode the packets it received by randomly choosing coefficients in a finite field Fq, then forwards it to the destination. Owing to the inherent errorprone nature of erasure channels, data packets received by the relay and the destination nodes may not be correct. We analyze the optimal throughput with respect to n, given a series of parameters and derive the upper and lower bounds of throughput performance. We also analyze the impact of the number of relays and the erasure probability on the throughput performance. Simulation results are well matched with the theoretical analysis.

• Heungwoo NAM
Type: LETTER
Subject area: Mobile Information Network and Personal Communications
2017 Volume E100.A Issue 7 Pages 1596-1600
Published: July 01, 2017
Released: July 01, 2017
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As autonomous underwater vehicles (AUVs) have been widely used to perform cooperative works with sensor nodes for data-gathering, the need for long-range AUVs has further grown to support the long-duration cooperation with sensor nodes. However, as existing data-gathering protocols for the cooperative works have not considered AUVs' energy consumption, AUVs can deplete their energy more quickly before fulfilling their missions. The objective of this work is to develop an AUV based data-gathering protocol that maximizes the duration for the cooperative works. Simulation results show that the proposed protocol outperforms existing protocols with respect to the long-range AUVs.