J-STAGE Home  >  Publications - Top  > Bibliographic Information

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Vol. E100.A (2017) No. 7 pp. 1496-1499



Special Section on Design Methodologies for System on a Chip

Approximate computing is considered as a promising approach to design of power- or area-efficient digital circuits. This paper proposes a systematic methodology for design and worst-case accuracy analysis of approximate array multipliers. Our methodology systematically designs a series of approximate array multipliers with different area, delay, power and accuracy characteristics so that an LSI designer can select the one which best fits to the requirements of her/his applications. Our experiments explore the trade-offs among area, delay, power and accuracy of the approximate multipliers.

Copyright © 2017 The Institute of Electronics, Information and Communication Engineers

Share this Article