IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Special Section on Design Methodologies for System on a Chip
A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers
Takahiro YAMAMOTOIttetsu TANIGUCHIHiroyuki TOMIYAMAShigeru YAMASHITAYuko HARA-AZUMI
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2017 Volume E100.A Issue 7 Pages 1496-1499

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Abstract

Approximate computing is considered as a promising approach to design of power- or area-efficient digital circuits. This paper proposes a systematic methodology for design and worst-case accuracy analysis of approximate array multipliers. Our methodology systematically designs a series of approximate array multipliers with different area, delay, power and accuracy characteristics so that an LSI designer can select the one which best fits to the requirements of her/his applications. Our experiments explore the trade-offs among area, delay, power and accuracy of the approximate multipliers.

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© 2017 The Institute of Electronics, Information and Communication Engineers
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