A Reference Voltage Buffer with Settling Boost Technique for a 12bit 18MHz Multibit/Stage Pipelined A/D Converter

Shunsuke OKURA; Tetsuro OKURA; Toru IDO; Kenji TANIGUCHI

doi:10.1587/transfun.E92.A.367

Special Section on Analog Circuit Techniques and Related Topics

A Reference Voltage Buffer with Settling Boost Technique for a 12bit 18MHz Multibit/Stage Pipelined A/D Converter

Shunsuke OKURA, Tetsuro OKURA, Toru IDO, Kenji TANIGUCHI

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Keywords: CMOS, pipelined ADC, settling, boost, low power

JOURNAL RESTRICTED ACCESS

2009 Volume E92.A Issue 2 Pages 367-373

DOI https://doi.org/10.1587/transfun.E92.A.367

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Abstract

A reference voltage buffer for a multibit/stage pipelined ADC is described, where a settling boost technique is used to improve the settling response of the pipelined stages. A 12bit 18MHz pipelined ADC with the buffer is designed and simulated based on a 0.35µm CMOS process. According to simulation results, the power consumed by the reference voltage buffer is reduced by 33% compared to that without the settling boost technique.

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