IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Volume E92.A , Issue 2
Showing 1-47 articles out of 47 articles from the selected issue
Special Section on Analog Circuit Techniques and Related Topics
  • Akira HYOGO
    2009 Volume E92.A Issue 2 Pages 349
    Published: February 01, 2009
    Released: February 01, 2009
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  • Ali M. NIKNEJAD, Ehsan ADABI, Babak HEYDARI, Mounir BOHSALI, Bagher AF ...
    Type: INVITED PAPER
    2009 Volume E92.A Issue 2 Pages 350-359
    Published: February 01, 2009
    Released: February 01, 2009
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    This paper highlights seven years of research at the Berkeley Wireless Research Center (BWRC) related to mm-wave electronics. Active and passive device design and layout, circuit approaches, and system architecture for short range mm-wave communication links will be discussed. The design of several key building blocks in a receiver front-end will be highlighted.
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  • Yasuhide KURAMOCHI, Akira MATSUZAWA, Masayuki KAWABATA
    Type: PAPER
    2009 Volume E92.A Issue 2 Pages 360-366
    Published: February 01, 2009
    Released: February 01, 2009
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    We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digital-to-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital control blocks has been fabricated in a 0.18-µm CMOS process and consumes 118µW at 1.8V power supply. Also, the active area of ADC core is realized to be 0.027mm2. The calibration improves the SNDR by 13.4dB and the SFDR by 21.0dB. The measured SNDR and SFDR at 1kHz input are 55.2dB and 73.2dB respectively.
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  • Shunsuke OKURA, Tetsuro OKURA, Toru IDO, Kenji TANIGUCHI
    Type: PAPER
    2009 Volume E92.A Issue 2 Pages 367-373
    Published: February 01, 2009
    Released: February 01, 2009
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    A reference voltage buffer for a multibit/stage pipelined ADC is described, where a settling boost technique is used to improve the settling response of the pipelined stages. A 12bit 18MHz pipelined ADC with the buffer is designed and simulated based on a 0.35µm CMOS process. According to simulation results, the power consumed by the reference voltage buffer is reduced by 33% compared to that without the settling boost technique.
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  • Koji ASAMI, Takahide SUZUKI, Hiroyuki MIYAJIMA, Tetsuya TAURA, Haruo K ...
    Type: PAPER
    2009 Volume E92.A Issue 2 Pages 374-380
    Published: February 01, 2009
    Released: February 01, 2009
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    One method for achieving high-speed waveform digitizing uses time-interleaved A-D Converters (ADCs). It is known that, in this method, using multiple ADCs enables sampling at a rate higher than the sampling rate of the ADC being used. Degradation of the dynamic range, however, results from such factors as phase error in the sampling clock applied to the ADC, and mismatched frequency characteristics among the individual ADCs. This paper describes a method for correcting these mismatches using a digital signal processing (DSP) technique for automatic test equipment applications. This method can be applied to any number of interleaved ADCs, and it does not require any additional hardware; good correction and improved accuracy can be obtained simply by adding a little to the computing overhead.
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  • Masahiro YOSHIOKA, Nobuo FUJII
    Type: PAPER
    2009 Volume E92.A Issue 2 Pages 381-388
    Published: February 01, 2009
    Released: February 01, 2009
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    This paper proposes a new charge pump to suppress spurious noise of phase-locked loops. The spurious noise is induced by charge injection generated from the parasitic capacitors associated with switches and the current-mismatch between the charging and discharging currents of the charge pump. A new charge pump is configured by adding an operational amplifier, a sample-and-hold circuit, and switches to a basic charge pump. During the idling time of the charge pump, the currents of the current sources are adjusted and the current-mismatch are reduced to 0.3%. Applying the proposed charge pump to a phase-locked loop, we can suppress the spurious noise by 18dB compared with a PLL using a basic one.
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  • Shu-Yu JIANG, Chan-Wei HUANG, Yu-Lung LO, Kuo-Hsing CHENG
    Type: PAPER
    2009 Volume E92.A Issue 2 Pages 389-400
    Published: February 01, 2009
    Released: February 01, 2009
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    Several problems in built-in-jitter-measurement (BIJM) system designs have been identified in recent years. The problems are associated with the external low-jitter sampling clock, chip area, timing resolution, or the measurement range via the process voltage temperature (PVT) variation effect. In this work, there are three proposed approaches and one conventioanl method that improve BIJM systems. For the system level, a proposed real equivalent-signal sampling technique is utilized to clear the requirement of the external low-jitter sampling clock. The proposed Vernier caliper structure is applied to reduce chip area cost for the designated timing resolution. At the circuit level, the proposed auto focus technique eliminates the PVT variation effect for the measurement range. The stepping scan technique is the conventional method that employed to minimize the area cost of counter circuits. All of these techniques were implemented in the 0.35µm CMOS process. Furthermore, these techniques are successfully verified in 14ps circuit resolution and a 500*750µm chip area for the 100-400MHz measurement range.
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  • Hirotaka SUGAWARA, Kenichi OKADA, Kazuya MASU
    Type: PAPER
    2009 Volume E92.A Issue 2 Pages 401-410
    Published: February 01, 2009
    Released: February 01, 2009
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    This paper proposes a novel wide-tunable CMOS low-noise amplifier (LNA) using a variable inductor. The variable inductance can be tuned by shielding the magnetic flux, which uses a metal plate above the inductor. The metal plate can be moved using a MEMS actuator. At the present time, the MEMS actuator has not been implemented yet. In this paper, we present a feasibility study on the proposed LNA using the variable inductor. The proposed LNA uses two variable inductors for input and output impedance matching-tuning. The LNA achieves a power gain (PG) of over 10dB at a tuning range of 1.6-3.2GHz.
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  • Shouhei KOUSAI, Mototsugu HAMADA, Rui ITO, Tetsuro ITAKURA
    Type: PAPER
    2009 Volume E92.A Issue 2 Pages 411-420
    Published: February 01, 2009
    Released: February 01, 2009
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    A novel automatic quality factor (Q) tuning scheme for an low-power and wideband active-RC filter is presented. Although Q-tuning is effective to reduce the power consumption of wideband active-RC filters, there are several problems since the Q-tuning normally relies on a magnitude locked loop (MLL). MLL is not accurate due to the amplitude detection circuits, and occupied area and power consumption tends to be large due to its complexity. In addition, flexibility to the reference signal may be the problem, since the reference signal which has a fixed accurate frequency is required. In order to solve these problems, we propose a Q-tuning scheme, which does not require a MLL. Therefore, proposed Q-tuning scheme has good accuracy, small die area, low power consumption and flexibility to the reference signal. In our proposed scheme, Q is tuned by adjusting the phase of an integrator to 90 degrees. The phase of an integrator is adjusted by detecting and controlling the oscillation frequency of a two-stage ring-integrator to the cutoff frequency of a filter, since the phase shift of an integrator is exactly 90 degrees at the oscillation frequency. The frequency is easily detected and controlled by counters and variable resistors, respectively. The Q-tuning circuit with a 5th-order Chebyshev LPF is implemented in a 0.13µm CMOS technology. The tuning circuit occupies 0.12mm2 and consumes 2.6mW from 1.2V supply.
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  • Kawori TAKAKUBO, Toru ETO, Hajime TAKAKUBO
    Type: PAPER
    2009 Volume E92.A Issue 2 Pages 421-429
    Published: February 01, 2009
    Released: February 01, 2009
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    Leakage current for MOSFET in off-state is one of the serious problems in charge-based analog circuits under low power supply. To suppress the leakage current, a method that a slight voltage is applied to source to accomplish reverse bias between source and bulk is proposed. The proposed bias condition, also other bias conditions, is analyzed by injection carrier density in p-n junction and surface carrier concentration in MOS diode in four-terminal MOSFET. Leakage current is modeled by combining the characteristics of p-n junction with MOS diode in MOSFET. The characteristics of MOSFET fabricated with a standard 0.18µm n-well CMOS technology are measured to investigate the basic principle. Measured leakage current fits to the theoretical leakage current exactly. The proposed slight bias to source terminal in MOSFET is proved most efficient to reduce the leakage current. Based on the proposed source bias condition, MOSFET switches with low leakage current under a single power supply are proposed.
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  • Dongsoo KIM, Jimin CHEON, Gunhee HAN
    Type: PAPER
    2009 Volume E92.A Issue 2 Pages 430-435
    Published: February 01, 2009
    Released: February 01, 2009
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    The performance of an analog winner-take-all (WTA) circuit is affected by the corner error and the offset error. Despite the fact that the corner error can be reduced with large transconductance of the transistor, the offset error caused by device mismatch has not been completely studied. This paper presents the complete offset error analysis, and proposes low offset design guidelines and an offset cancellation scheme. The experimental results show good agreement with the theoretical analysis and the drastic improvement of the offset error.
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  • Taichi OGAWA, Tetsuya HIROSE, Tetsuya ASAI, Yoshihito AMEMIYA
    Type: PAPER
    2009 Volume E92.A Issue 2 Pages 436-442
    Published: February 01, 2009
    Released: February 01, 2009
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    A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.
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  • Kawori TAKAKUBO, Hajime TAKAKUBO
    Type: PAPER
    2009 Volume E92.A Issue 2 Pages 443-450
    Published: February 01, 2009
    Released: February 01, 2009
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    A wide range CMOS voltage detector with low current consumption consisting of CMOS inverters operating in both weak inversion and saturation region is proposed. A terminal of power supply for CMOS inverter can be expanded to a signal input terminal. A voltage-detection point and hysteresis characteristics of the proposed circuit can be designed by geometrical factor in MOSFET and an external bias voltage. The core circuit elements are fabricated in standard 0.18µm CMOS process and measured to confirm the operation. The detectable voltage is from 0.3V to 1.8V. The current consumption of voltage detection, standby current, is changed from 65pA for Vin =0.3V to 5.5µA for Vin =1.8V. The thermal characteristics from 250K to 400K are also considered. The measured temperature coefficient of the proposed voltage-detector core operating in weak inversion region is 4ppm/K and that in saturation region is 10ppm/K. The proposed voltage detector can be implemented with tiny chip area and is expected to an on-chip voltage detector of power supply for mobile application systems.
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  • Santhos A. WIBOWO, Zhang TING, Masashi KONO, Tetsuya TAURA, Yasunori K ...
    Type: LETTER
    2009 Volume E92.A Issue 2 Pages 451-455
    Published: February 01, 2009
    Released: February 01, 2009
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    This letter presents an analysis of characteristics of multiphase buck converters with coupled inductors. We derive equivalent inductances that provide both low per-phase steady-state ripple current and fast transient response. The characteristics of coupled-inductor circuits — low per-phase ripple current and fast response — were examined and verified by circuit simulation and experiments.
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  • Yasuyuki MATSUYA, Takahiro MESUDA
    Type: LETTER
    2009 Volume E92.A Issue 2 Pages 456-458
    Published: February 01, 2009
    Released: February 01, 2009
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    We propose a stereo transmission technique using infrared rays and pulse density modulation (PDM) for digital wireless audio headphone systems. The main feature of the proposed technique is the use of two channels for transmission: the PDM data channel and the synchronized clock channel. This technique improves receiver characteristics to a noise floor of -80dB and a second distortion of 62dB and achieves a very low power consumption of 3.5mW.
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Regular Section
  • Hidehiro NAKANO, Akihide UTANI, Arata MIYAUCHI, Hisao YAMAMOTO
    Type: PAPER
    Subject area: Nonlinear Problems
    2009 Volume E92.A Issue 2 Pages 459-466
    Published: February 01, 2009
    Released: February 01, 2009
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    Wireless sensor networks (WSNs) have attracted a significant amount of interest from many researchers because they have great potential as a means of obtaining information of various environments remotely. WSNs have a wide range of applications, such as natural environmental monitoring in forest regions and environmental control in office buildings. In WSNs, hundreds or thousands of micro-sensor nodes with such resource limitations as battery capacity, memory, CPU, and communication capacity are deployed without control in a region and used to monitor and gather sensor information of environments. Therefore, a scalable and efficient network control and/or data gathering scheme for saving energy consumption of each sensor node is needed to prolong WSN lifetime. In this paper, assuming that sensor nodes synchronize to intermittently communicate with each other only when they are active for realizing the long-term employment of WSNs, we propose a new synchronization scheme for gathering sensor information using chaotic pulse-coupled neural networks (CPCNN). We evaluate the proposed scheme using computer simulations and discuss its development potential. In simulation experiments, the proposed scheme is compared with a previous synchronization scheme based on a pulse-coupled oscillator model to verify its effectiveness.
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  • Natsumi HIRAKAWA, Kunihiro FUJIYOSHI
    Type: PAPER
    Subject area: VLSI Design Technology and CAD
    2009 Volume E92.A Issue 2 Pages 467-474
    Published: February 01, 2009
    Released: February 01, 2009
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    Symmetry constrains are the constraints that the given cells should be placed symmetrically in design of analog ICs. We use O-tree to represent placements and propose a decoding algorithm which can obtain one of the minimum placements satisfying the constraints. The decoding algorithm uses linear programming, which is too much time consuming. Therefore we propose a graph based method to recognize if there exists no placement satisfying both the given symmetry and O-tree constraints, and use the method before application of linear programming. The effectiveness of the proposed method was shown by computational experiments.
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  • Hong Bo CHE, Hyoun Soo PARK, Jin Wook KIM, Young Hwan KIM
    Type: PAPER
    Subject area: VLSI Design Technology and CAD
    2009 Volume E92.A Issue 2 Pages 475-480
    Published: February 01, 2009
    Released: February 01, 2009
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    The authors present R2Power, an effective approach to the realizable reduction of RC networks with independent current sources. The proposed approach is based on the entrywise perturbation theory for diagonally dominant M-matrices. The accuracy of the node voltages of the reduced network, as compared to those of the original network, is maintained on the order of the entrywise perturbation performed during reduction. R2Power can be used to reduce the size of RC networks used to model the power networks of SoCs, for efficient IR-drop analysis. Experiments showed that R2Power reduced the size of industrial examples by more than 95%, with maximum relative node voltage errors of less than 0.012%.
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  • Nam-Geun KIM, Youngsu PARK, Jong-Wook KIM, Eunsu KIM, Sang Woo KIM
    Type: PAPER
    Subject area: Numerical Analysis and Optimization
    2009 Volume E92.A Issue 2 Pages 481-492
    Published: February 01, 2009
    Released: February 01, 2009
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    In this paper, we present a recently developed pattern search method called Genetic Pattern Search algorithm (GPSA) for the global optimization of cost function subject to simple bounds. GPSA is a combined global optimization method using genetic algorithm (GA) and Digital Pattern Search (DPS) method, which has the digital structure represented by binary strings and guarantees convergence to stationary points from arbitrary starting points. The performance of GPSA is validated through extensive numerical experiments on a number of well known functions and on robot walking application. The optimization results confirm that GPSA is a robust and efficient global optimization method.
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  • Takeyuki TAMURA, Tatsuya AKUTSU
    Type: PAPER
    Subject area: Algorithms and Data Structures
    2009 Volume E92.A Issue 2 Pages 493-501
    Published: February 01, 2009
    Released: February 01, 2009
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    The Boolean network (BN) is a mathematical model of genetic networks. It is known that detecting a singleton attractor, which is also called a fixed point, is NP-hard even for AND/OR BNs (i.e., BNs consisting of AND/OR nodes), where singleton attractors correspond to steady states. Though a naive algorithm can detect a singleton attractor for an AND/OR BN in O(n 2n) time, no O((2-ε)n) (ε > 0) time algorithm was known even for an AND/OR BN with non-restricted indegree, where n is the number of nodes in a BN. In this paper, we present an O(1.787n) time algorithm for detecting a singleton attractor of a given AND/OR BN, along with related results. We also show that detection of a singleton attractor in a BN with maximum indegree two is NP-hard and can be polynomially reduced to a satisfiability problem.
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  • Miyuki UNO, Tomoharu KAWANO, Mikio KANO
    Type: PAPER
    Subject area: Algorithms and Data Structures
    2009 Volume E92.A Issue 2 Pages 502-507
    Published: February 01, 2009
    Released: February 01, 2009
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    Assume that 2m red points and 2n blue points are given on the lattice Z2 in the plane R2. We show that if they are in general position, that is, if at most one point lies on each vertical line and horizontal line, then there exists a rectangular cut that bisects both red points and blue points. Moreover, if they are not in general position, namely if some vertical and horizontal lines may contain more than one point, then there exists a semi-rectangular cut that bisects both red points and blue points. We also show that these results are best possible in some sense. Moreover, our proof gives O(N log N), N = 2m + 2n, time algorithm for finding the desired cut.
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  • Masataka AKANE, Yasuyuki NOGAMI, Yoshitaka MORIKAWA
    Type: PAPER
    Subject area: Cryptography and Information Security
    2009 Volume E92.A Issue 2 Pages 508-516
    Published: February 01, 2009
    Released: February 01, 2009
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    This paper presents implementation techniques of fast Ate pairing of embedding degree 12. In this case, we have no trouble in finding a prime order pairing friendly curve E such as the Barreto-Naehrig curve $y^2=x^3+a, a\\in\\Fp{}$. For the curve, an isomorphic substitution from $\\Gii\\subset \\EFpxii$ into $\\Gii'$ in subfield-twisted elliptic curve $\\EdFpii$ speeds up scalar multiplications over $\\Gii$ and wipes out denominator calculations in Miller's algorithm. This paper mainly provides about 30% improvement of the Miller's algorithm calculation using proper subfield arithmetic operations. Moreover, we also provide the efficient parameter settings of the BN curves. When p is a 254-bit prime, the embedding degree is 12, and the processor is Pentium4 (3.6GHz), it is shown that the proposed algorithm computes Ate pairing in 13.3 milli-seconds including final exponentiation.
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  • Kazuhiko MINEMATSU, Toshiyasu MATSUSHIMA
    Type: PAPER
    Subject area: Cryptography and Information Security
    2009 Volume E92.A Issue 2 Pages 517-524
    Published: February 01, 2009
    Released: February 01, 2009
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    This paper describes an extension of XEX* mode, which is a method to convert a block cipher into a tagged tweakable block cipher, a notion introduced by Rogaway in 2004 as an extension of the tweakable block cipher by Liskov et al. Our extension attaches an additional encryption function to the original XEX*, which has some limitation but is slightly faster than the encryption implemented by XEX*. We prove our scheme's security in a general form, where the offset function, a key component of our construction, is not restricted to the one used by XEX*. We also provide some applications of our result, in particular to OCB 2.0, an authenticated encryption based on XEX*.
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  • Masashi NAITO, Shun WATANABE, Ryutaroh MATSUMOTO, Tomohiko UYEMATSU
    Type: PAPER
    Subject area: Information Theory
    2009 Volume E92.A Issue 2 Pages 525-534
    Published: February 01, 2009
    Released: February 01, 2009
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    We consider the problem of secret key agreement in Gaussian Maurer's Model. In Gaussian Maurer's model, legitimate receivers, Alice and Bob, and a wire-tapper, Eve, receive signals randomly generated by a satellite through three independent memoryless Gaussian channels respectively. Then Alice and Bob generate a common secret key from their received signals. In this model, we propose a protocol for generating a common secret key by using the result of soft-decision of Alice and Bob's received signals. Then, we calculate a lower bound on the secret key rate in our proposed protocol. As a result of comparison with the protocol that only uses hard-decision, we found that the higher rate is obtained by using our protocol.
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  • Wenjie JIANG, Yusuke ASAI, Satoru AIKAWA, Yasutaka OGAWA
    Type: PAPER
    Subject area: Communication Theory and Signals
    2009 Volume E92.A Issue 2 Pages 535-546
    Published: February 01, 2009
    Released: February 01, 2009
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    The wireless systems that establish multiple input multiple output (MIMO) channels through multiple antennas at both ends of the communication link, have been proved to have tremendous potential to linearly lift the capacity of conventional scalar channel. In this paper, we present two efficient decision feedback equalization algorithms that achieve optimal and suboptimal detection order in MIMO spatial multiplexing systems. The new algorithms combine the recursive matrix inversion and ordered QR decomposition approaches, which are developed for nulling cancellation interaface Bell Labs layered space time (BLAST) and back substitution interface BLAST. As a result, new algorithms achieve total reduced complexities in frame based transmission with various payload lengths compared with the earlier methods. In addition, they enable shorter detection delay by carrying out a fast hybrid preprocessing. Moreover, the operation precision insensitivity of order optimization greatly relaxes the word length of matrix inversion, which is the most computational intensive part within the MIMO detection task.
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  • Sangchoon KIM, Jinyoung AN
    Type: PAPER
    Subject area: Spread Spectrum Technologies and Applications
    2009 Volume E92.A Issue 2 Pages 547-555
    Published: February 01, 2009
    Released: February 01, 2009
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    In this paper, the impacts of using multiple transmit antennas under doubly correlated MIMO channels on CDMA uplink code acquisition is studied. The performance of a MIMO code acquisition system is analyzed by considering spatial fading correlations, which depend on antenna spacing and azimuth spread at both MS and BS. The detection performance and mean acquisition time in the presence of spatially correlated MIMO channel are presented on a frequency selective fading channel and compared with the cases of spatial fading decorrelation via numerical evaluation. It is observed that the acquisition performance relies on the degree of spatial fading correlations. In addition, it is surprisingly seen that a MIMO code acquisition system provides worse performance than SIMO.
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  • Do Nyeon KIM, Yoonsik CHOE, K.R. RAO
    Type: PAPER
    Subject area: Image
    2009 Volume E92.A Issue 2 Pages 556-562
    Published: February 01, 2009
    Released: February 01, 2009
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    Fast schemes for compressed-domain image size change, are proposed. Fast Winograd DCTs are applied to resizing images by a factor of two to one. First, we speed up the DCT domain downsampling scheme which uses the bilinear interpolation. Then, we speed up other image resizing schemes which use DCT lowpass truncated approximations. The schemes proposed here reduce the computational complexities significantly, while there is no difference in the overall quality of the images compared to previous works.
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  • Kuo-Cheng LIU
    Type: PAPER
    Subject area: Image
    2009 Volume E92.A Issue 2 Pages 563-576
    Published: February 01, 2009
    Released: February 01, 2009
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    In this paper, a perceptually adaptive watermarking scheme for color images is proposed in order to achieve robustness and transparency. A new just noticeable distortion (JND) estimator for color images is first designed in the wavelet domain. The key issue of the JND model is to effectively integrate visual masking effects. The estimator is an extension to the perceptual model that is used in image coding for grayscale images. Except for the visual masking effects given coefficient by coefficient by taking into account the luminance content and the texture of grayscale images, the crossed masking effect given by the interaction between luminance and chrominance components and the effect given by the variance within the local region of the target coefficient are investigated such that the visibility threshold for the human visual system (HVS) can be evaluated. In a locally adaptive fashion based on the wavelet decomposition, the estimator applies to all subbands of luminance and chrominance components of color images and is used to measure the visibility of wavelet quantization errors. The subband JND profiles are then incorporated into the proposed color image watermarking scheme. Performance in terms of robustness and transparency of the watermarking scheme is obtained by means of the proposed approach to embed the maximum strength watermark while maintaining the perceptually lossless quality of the watermarked color image. Simulation results show that the proposed scheme with inserting watermarks into luminance and chrominance components is more robust than the existing scheme while retaining the watermark transparency.
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  • Tomoki HIRAMATSU, Takahiro OGAWA, Miki HASEYAMA
    Type: PAPER
    Subject area: Image
    2009 Volume E92.A Issue 2 Pages 577-584
    Published: February 01, 2009
    Released: February 01, 2009
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    In this paper, a Kalman filter-based method for restoration of video images acquired by an in-vehicle camera in foggy conditions is proposed. In order to realize Kalman filter-based restoration, the proposed method clips local blocks from the target frame by using a sliding window and regards the intensities in each block as elements of the state variable of the Kalman filter. Furthermore, the proposed method designs the following two models for restoration of foggy images. The first one is an observation model, which represents a fog deterioration model. The proposed method automatically determines all parameters of the fog deterioration model from only the foggy images to design the observation model. The second one is a non-linear state transition model, which represents the target frame in the original video image from its previous frame based on motion vectors. By utilizing the observation and state transition models, the correlation between successive frames can be effectively utilized for restoration, and accurate restoration of images obtained in foggy conditions can be achieved. Experimental results show that the proposed method has better performance than that of the traditional method based on the fog deterioration model.
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  • Yoko UWATE, Yoshifumi NISHIO, Ruedi STOOP
    Type: PAPER
    Subject area: Neural Networks and Bioengineering
    2009 Volume E92.A Issue 2 Pages 585-593
    Published: February 01, 2009
    Released: February 01, 2009
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    Durability describes the ability of a device to operate properly in imperfect conditions. We have recently proposed a novel neural network structure called an “Affordable Neural Network” (AfNN), in which affordable neurons of the hidden layer are considered as the elements responsible for the robustness property as is observed in human brain function. Whereas earlier we have shown that AfNNs can still generalize and learn, here we show that these networks are robust against damages occurring after the learning process has terminated. The results support the view that AfNNs embody the important feature of durability. In our contribution, we investigate the durability of the AfNN when some of the neurons in the hidden layer are damaged after the learning process.
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  • Shangce GAO, Qiping CAO, Catherine VAIRAPPAN, Jianchen ZHANG, Zheng TA ...
    Type: PAPER
    Subject area: Neural Networks and Bioengineering
    2009 Volume E92.A Issue 2 Pages 594-603
    Published: February 01, 2009
    Released: February 01, 2009
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    This paper describes an improved local search method for synthesizing arbitrary Multiple-Valued Logic (MVL) function. In our approach, the MVL function is mapped from its algebraic presentation (sum-of-products form) on a multiple-layered network based on the functional completeness property. The output of the network is evaluated based on two metrics of correctness and optimality. A local search embedded with chaotic dynamics is utilized to train the network in order to minimize the MVL functions. With the characteristics of pseudo-randomness, ergodicity and irregularity, both the search sequence and solution neighbourhood generated by chaotic variables enables the system to avoid local minimum settling and improves the solution quality. Simulation results based on 2-variable 4-valued MVL functions and some other large instances also show that the improved local search learning algorithm outperforms the traditional methods in terms of the correctness and the average number of product terms required to realize a given MVL function.
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  • Kunihiko HIRAISHI, Petr KUCERA
    Type: PAPER
    Subject area: Concurrent Systems
    2009 Volume E92.A Issue 2 Pages 604-610
    Published: February 01, 2009
    Released: February 01, 2009
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    Software model checking is typically applied to components of large systems. The assumption generation is the problem of finding the least restrictive environment in which the components satisfy a given safety property. There is an algorithm to compute the environment for properties given as a regular language. In this paper, we propose a general scheme for computing the assumption even for non-regular properties, and show the uniqueness of the least restrictive assumption for any class of languages. In general, dealing with non-regular languages may fall into undecidability of problems. We also show a method to compute assumptions based on visibly pushdown automata and their finite-state abstractions.
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  • Hirosato SEKI, Hiroaki ISHII
    Type: PAPER
    Subject area: General Fundamentals and Boundaries
    2009 Volume E92.A Issue 2 Pages 611-617
    Published: February 01, 2009
    Released: February 01, 2009
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    Fuzzy inference has played a significant role in many applications. Although the simplified fuzzy inference method is currently mostly used, the problem is that the number of fuzzy rules becomes very huge and so the setup and adjustment of fuzzy rules become difficult. On the other hand, Yubazaki et al. have proposed a “single input rule modules connected fuzzy inference method” (SIRMs method) whose final output is obtained by summarizing the product of the importance degrees and the inference results from single input fuzzy rule module. Seki et al. have shown that the simplified fuzzy inference method and the SIRMs method are equivalent when the sum of diagonal elements in rules of the simplified fuzzy inference method is equal to that of cross diagonal elements. This paper clarifies the conditions for the infimum and supremum of the fuzzy inference method using the single input type fuzzy inference method, from the view point of fuzzy inference.
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  • Minoru SAKAIRI, Ayako NISHIMURA, Daisuke SUZUKI
    Type: PAPER
    Subject area: General Fundamentals and Boundaries
    2009 Volume E92.A Issue 2 Pages 618-629
    Published: February 01, 2009
    Released: February 01, 2009
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    For the purpose of the application of odor to information technology, we have developed an odor-emitting apparatus coupled with chemical capsules made of alginic acid polymer. This apparatus consists of a chemical capsule cartridge including chemical capsules of odor ingredients, valves to control odor emission, and a temperature control unit. Different odors can be easily emitted by using the apparatus. We have developed an integrated system of vision, audio and olfactory information in which odor strength can be controlled coinciding with on-screen moving images based on analytical results from the odor scanner.
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  • Sang-Kyun KIM, Joon-Hyuk CHANG
    Type: LETTER
    Subject area: Speech and Hearing
    2009 Volume E92.A Issue 2 Pages 630-632
    Published: February 01, 2009
    Released: February 01, 2009
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    In this letter, we propose a novel approach to speech/music classification based on the support vector machine (SVM) to improve the performance of the 3GPP2 selectable mode vocoder (SMV) codec. We first analyze the features and the classification method used in real time speech/music classification algorithm in SMV, and then apply the SVM for enhanced speech/music classification. For evaluation of performance, we compare the proposed algorithm and the traditional algorithm of the SMV. The performance of the proposed system is evaluated under the various environments and shows better performance compared to the original method in the SMV.
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  • Kyo TAKAHASHI, Shingo SATO, Tadamichi KUDO, Yoshitaka TSUNEKAWA
    Type: LETTER
    Subject area: Digital Signal Processing
    2009 Volume E92.A Issue 2 Pages 633-637
    Published: February 01, 2009
    Released: February 01, 2009
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    In this report, we propose a high-performance pipelined VLSI architecture of the LMS adaptive filter derived by a cut-set retiming technique. The proposed architecture has a peculiar pipelined form with 3 adaptation delays, and the FIR filter portion has a peculiar class of the transposed form providing a minimum output latency and coefficient delay. Both the delays, the adaptation delay and coefficient delay, are compensated by a look-ahead conversion. A new high-speed 4-input and 2-output CSA type adder with a small hardware is employed. The proposed architecture can achieve a good convergence property, high-sampling rate, minimum output latency, small hardware, and lower power dissipation, simultaneously, and is very suitable to implement on the VLSI.
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  • Kiyotaka YAMAMURA, Koki SUDA
    Type: LETTER
    Subject area: Nonlinear Problems
    2009 Volume E92.A Issue 2 Pages 638-642
    Published: February 01, 2009
    Released: February 01, 2009
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    An efficient and practical algorithm is proposed for finding all DC solutions of nonlinear circuits. This algorithm is based on interval analysis and linear programming techniques. The proposed algorithm is very efficient and can be easily implemented by using the free package GLPK (GNU Linear Programming Kit). By numerical examples, it is shown that the proposed algorithm could find all solutions of a system of 2000 nonlinear circuit equations in practical computation time.
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  • Jong-Ho ROH, Minje JUN, Kwanhu BANG, Eui-Young CHUNG
    Type: LETTER
    Subject area: VLSI Design Technology and CAD
    2009 Volume E92.A Issue 2 Pages 643-647
    Published: February 01, 2009
    Released: February 01, 2009
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    Jitter is the variation of latencies, when real-time Intellectual Properties (IPs) are accessing data from the data storages. It is a critical factor for such IPs from the Quality-of-Service (QoS) perspective. Jitter of a real-time IP can be measured by how frequently it experiences the underflows and overflows from its data queue in read mode and write mode, respectively. Such failures critically depend on the bus arbitration scheme which determines the bus acquisition order of IPs. The proposed idea allows IPs to inform the bus arbiter of the status of their data buffers when they assert bus requests. Such information helps the bus arbiter to determine the bus acquisition order while greatly reducing the jitter. The experimental results show that our method effectively eliminates the overflows and underflows of real-time IPs by dynamically preempting the jitter-critical bus requests.
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  • Hong Bo CHE, Jin Wook KIM, Tae Il BAE, Young Hwan KIM
    Type: LETTER
    Subject area: VLSI Design Technology and CAD
    2009 Volume E92.A Issue 2 Pages 648-651
    Published: February 01, 2009
    Released: February 01, 2009
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    A new acceleration scheme that decreases the number of required iterations in relaxation methodology is proposed. The proposed scheme uses dynamic error prediction of an improved approximation to the solution during an iterative computation. The proposed scheme's application to circuit simulations required an average of 67.3% fewer iterations compared to un-accelerated relaxation methods.
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  • Alexander M. ZEMLIAK
    Type: LETTER
    Subject area: VLSI Design Technology and CAD
    2009 Volume E92.A Issue 2 Pages 652-657
    Published: February 01, 2009
    Released: February 01, 2009
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    The process of designing analogue circuits is formulated as a controlled dynamic system. For analysis of such system's properties it is suggested to use the concept of Lyapunov's function for a dynamic system. Various forms of Lyapunov's function are suggested. Analyzing the behavior of Lyapunov's function and its first derivative allowed us to determine significant correlation between this function's properties and processor time used to design the circuit. Numerical results prove the possibility of forecasting the behavior of various designing strategies and processor time based on the properties of Lyapunov's function for the process of designing the circuit.
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  • José CARRIJO, Rafael TONICELLI, Hideki IMAI, Anderson C.A. NASC ...
    Type: LETTER
    Subject area: Cryptography and Information Security
    2009 Volume E92.A Issue 2 Pages 658-662
    Published: February 01, 2009
    Released: February 01, 2009
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    We present a very simple probabilistic, passive attack against the protocols HB and HB+. Our attack presents some interesting features: it requires less captured transcripts of protocol executions when compared to previous results; It makes possible to trade the amount of required transcripts for computational complexity; the value of noise used in the protocols HB and HB+ need not be known.
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  • Zhixiong CHEN, Xiaoni DU, Rong SUN
    Type: LETTER
    Subject area: Cryptography and Information Security
    2009 Volume E92.A Issue 2 Pages 663-667
    Published: February 01, 2009
    Released: February 01, 2009
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    Based on the cyclotomy classes of extension fields, a family of binary cyclotomic sequences are constructed and their pseudorandom measures (i.e., the well-distribution measure and the correlation measure of order k) are estimated using certain exponential sums. A lower bound on the linear complexity profile is also presented in terms of the correlation measure.
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  • Xiaoni DU, Zhixiong CHEN, Ailing SHI, Rong SUN
    Type: LETTER
    Subject area: Information Theory
    2009 Volume E92.A Issue 2 Pages 668-670
    Published: February 01, 2009
    Released: February 01, 2009
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    A new class of sextic residue sequences of period prime p = 4u2 + 27 = 6f + 1 ≡ 3 (mod 8) are presented. Their trace function representations are determined. And the exact value of the linear complexity is derived from the trace function representations. The result indicates that the new sextic sequences are quite good from the linear complexity viewpoint.
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  • Hitoshi TOKUSHIGE, Marc FOSSORIER, Tadao KASAMI
    Type: LETTER
    Subject area: Coding Theory
    2009 Volume E92.A Issue 2 Pages 671-672
    Published: February 01, 2009
    Released: February 01, 2009
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    This letter deals with an iterative decoding algorithm (IDA) for product codes. In the IDA, a soft-input and output iterative bounded-distance and encoding-based decoding algorithm is used for the component codes. Simulation results over an AWGN channel with BPSK modulation is presented and show the effectiveness of the IDA.
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  • Jaewon KIM, Yoan SHIN, Wonjin SUNG
    Type: LETTER
    Subject area: Communication Theory and Signals
    2009 Volume E92.A Issue 2 Pages 673-676
    Published: February 01, 2009
    Released: February 01, 2009
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    In this letter, we present an exact analytic expression for the maximum signal-to-interference ratio (SIR) for receivers communicating with multiple transmitting nodes over a general time-varying channel, where one of the nodes is chosen as a desired signal source based on the instantaneous channel condition and the other nodes act as interference sources. As an illustrative example, the maximum SIR distribution of a mobile receiver surrounded by three base stations (BS) is determined in a closed-form formula for Rayleigh fading channels, and its accuracy is confirmed using simulation results.
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  • Soon-Woo LEE, Young-Jin PARK, Yong-Hwa KIM, Kwan-Ho KIM
    Type: LETTER
    Subject area: Mobile Information Network and Personal Communications
    2009 Volume E92.A Issue 2 Pages 677-680
    Published: February 01, 2009
    Released: February 01, 2009
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    This letter proposes an adaptive threshold control algorithm for a low complex noncoherent IR-UWB receiver using a 1-bit ADC. To estimate and control a threshold level in the noncoherent IR-UWB receiver, it uses binary output of the 1-bit ADC instead of energy level of received signals using a high resolution ADC, which reduces hardware complexity of the receiver. Theoretical performance evaluation and computer simulation demonstrates that the performance of the proposed algorithm is similar to that of theoretically optimum one.
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  • Wooram LEE, Gunhaeng HEO, Kwanho YOU
    Type: LETTER
    Subject area: Measurement Technology
    2009 Volume E92.A Issue 2 Pages 681-684
    Published: February 01, 2009
    Released: February 01, 2009
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    The heterodyne laser interferometer acts as an ultra-precise measurement apparatus in semiconductor manufacture. However the periodical nonlinearity property caused from frequency cross-talk is an obstacle to improve the high measurement accuracy in nanometer scale. In order to minimize the nonlinearity error of the heterodyne interferometer, we propose a frequency cross-talk compensation algorithm using an artificial intelligence method. The feedforward neural network trained by back-propagation compensates the nonlinearity error and regulates to minimize the difference with the reference signal. With some experimental results, the improved accuracy is proved through comparison with the position value from a capacitive displacement sensor.
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