IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Special Section on Design Methodologies for System on a Chip
Bi-Partitioning Based Multiplexer Network for Field-Data Extractors
Koki ITOKazushi KAWAMURAYutaka TAMIYAMasao YANAGISAWANozomu TOGAWA
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2016 Volume E99.A Issue 7 Pages 1410-1414

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Abstract

An (M,N)-field-data extractor reads out any consecutive N bytes from an M-byte register by connecting its input/output using a multiplexer (MUX) network. It is used in packet analysis and/or stream data processing for video/audio data. In this letter, we propose an efficient MUX network for an (M,N)-field-data extractor. By bi-partitioning a simple MUX network into an upper one and a lower one, we can theoretically reduce the number of required MUXs without increasing the MUX network depth. Experimental results show that we can reduce the gate count by up to 92% compared to a naive approach.

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© 2016 The Institute of Electronics, Information and Communication Engineers
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