Article ID: 2025VLP0005
In recent years, Built-In Self-Test (BIST) techniques have been widely used to reduce manufacturing test cost in large scale integrated circuits. However, it is difficult to achieve complete fault coverage on BIST, which uses pseudo-random test patterns, due to the presence of random pattern resistant faults. One-pass seed generation methods for a single target fault using satisfiability problem have been proposed as an efficient seed generation method. However, to target a single fault might require many seeds to obtain complete fault coverage. We propose a multiple target seed generation method for random pattern resistant stuck-at faults on BIST using pseudo-Boolean optimization and a compatible fault set to achieve complete fault coverage with the smaller number of seeds. The number of seeds is reduced by maximizing the number of detected faults per seed. Experimental results for ISCAS'89 benchmark circuits and ITC'99 benchmark circuits show that the proposed method could reduce the number of seeds by 49.69 % on average and by 76.72 % on maximum.
