ReRAM resistance design of LRS and HRS for ultrahigh-capacity digital memory and analog Computation-in-Memory

Abstract

This paper proposes a ReRAM resistance design for ultrahigh-capacity digital memory and analog Computation-in-Memory (CiM). The read-out current of the bit-line is degraded by the interconnection resistance of the bit-line due to IR drop. The bit-line current formulation reveals that the ReRAM resistance should be set as high as 1.0×10⁵ Ω for the high-capacity digital ReRAM memory. In addition, the ReRAM resistance of LRS and HRS is designed as 1.0×10⁵ Ω and 1.0×10⁹ Ω for the high-capacity analog ReRAM CiM.