We propose a novel annealing technique for process damage recovery to improve the dark characteristics for CMOS image sensor without deteriorating the transistor performances. Microwave annealing (MWA) has been studied as an alternative annealing technique for diffusion-less dopant activation and recovery of process damage in advanced CMOS technology. We employed MWA technique to repair crystalline defects for the purpose of better dark characteristics in CMOS image sensor (CIS) process. We demonstrate that MWA can actualize the effect of recovering ion-implantation damage equivalent to conventional furnace annealing (FA) with lower temperature annealing. MWA can recover the process damage without transistor performance deterioration to replace the conventional annealing. MWA is promising technique for repairing crystalline defects in high performance image sensing devices with high frame rate, low power and excellent dark characteristics.

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In this paper, we describe an analysis methodology of the components of floating diffusion (FD) capacitance (C_FD) using the developed test element group (TEG) and propose a C_FD reduction technology for photon-countable sensitivity. By analyzing the components of C_FD, it was confirmed that the sum of them agreed well with C_FD obtained by the photoelectric conversion characteristic in the image sensor and both the gate overlap capacitance and the p-n junction capacitance were large. The C_FD reduction technology based on the result of analysis was applied to the FD and pixel source follower (SF). This technology is characterized by omitting lightly doped drain (LDD) implantation process, shallow and low concentration diffusion layer, and non-channel stop. Applying the reduction technology, we designed and fabricated a CMOS image sensor chip using 0.18μm 1-Poly-Si 5-Metal CMOS process technology with pinned photodiode (PD). It exhibited C_FD of 0.66fF, conversion gain (CG) of 243μV/e- and input referred noise of 0.46e-_rms.

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Floating capacitor load readout operation for small, low power consumption and high S/N ratio CMOS image sensors and its effects are demonstrated. This readout operation utilizes a floating capacitor load instead of a constant current load as pixel SF driver, and the parasitic capacitor of pixel output vertical signal line as column sample/hold capacitor. Using a 0.18 μm CMOS image sensor technology, two CMOS image sensors were fabricated to verify the effects. The ratio of pixel area to the total effective area is over 92 %. The power consumption for pixel signal readout and pixel readout noise were decreased by over 97 % and 63.8 %, respectively. Also a higher readout gain and a wider linear response range were obtained. Furthermore, it was confirmed that this readout operation becomes more advantageous when decreasing the power supply voltage, which is favorable for ultra-low power sensor network system applications.

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A high QE and high readout speed ultraviolet-visible-near infrared (UV-VIS-NIR) light waveband linear photodiode array (PDA) is demonstrated in this paper. For the developed 1024 pixel PDA with the pixel size of 25 μm^H × 2500 μm^V, seven types of high transmittance optical layers were introduced for multiply divided pixel groups to achieve high QE for receiving light waveband and multiple transfer gates were placed along the long side of PD to improve readout speed. The fabricated PDA exhibited an average QE of 70 % for 200-800 nm and 80 % for 200-320 nm wavebands, the full well capacity (FWC) of over 70 pC and the line scan period of 0.33 msec simultaneously. The condition of top surface dopant concentration of the surface p⁺ layer of photodiode (PD) to prevent sensitivity degradation due to deuterium lamp irradiation was also clarified.

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The structure and performances of a CMOS image sensor fabricated by integrating technologies in a series of process flow that achieve wide spectral response, high robustness to ultraviolet (UV) light, high conversion gain (CG) and high full well capacity (FWC) is described. For PD junction formation, a high concentration p⁺ layer with steep dopant concentration profile was formed on a thick p-epitaxial layer. The concentration of the surface p+ layer was tuned sufficiently high in order to maintain the high UV light sensitivity and dark current against the deuterium lamp irradiation. For the FD structure, a lightly doped drain implantation before sidewall formation was omitted to reduce gate overlap capacitance. A CMOS image sensor using a 0.18 μm CMOS process technology achieved a high CG of 240 μV/e^–, a high FWC of 200 ke^–, a wide spectral response for 190-1000 nm and a high robustness to deuterium lamp irradiation stress.

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In this paper, we describe a device structure and optical design for a CMOS image sensor with phase-difference detection photodiodes (PD) for autofocus (AF) function. The individual pixel of this image sensor is composed of two horizontally displaced PDs separated by a PN junction. All the effective pixels function as both the imaging and the phase-difference detection AF (PDAF). We have realized a low dark random noise (1.8e- at 1PD, 2.5e- at 1pixel) and high sensitivity (78Ke-/lx.sec at 1green pixel) image sensor with the imaging and the PDAF functions in all the effective pixels.

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We have developed a 3D stacked 16Mpixel global-shutter CMOS image sensor with pixel level interconnections using four million micro bumps. The four photodiodes in the unit pixel circuit on the top substrate share one micro-bump interconnection in a 7.6μm pitch. Each signal of the photodiodes is transferred to the corresponding storage node on the bottom substrate via the interconnection to achieve a global-shutter function. The ratio of the parasitic light sensitivity of an in-pixel storage node and the light sensitivity of a photodiode is –180dB with a 3.8μm pixel. In addition, we discuss further improvement to reduce noise figure in global-shutter image sensors.

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We have developed a 1/1.7-inch 20Mpixel back-illuminated stacked CMOS image sensor with multi-functional modes which are parallel multiple sampling, the two simultaneous output streams and data compression. This sensor has achieved a RMS random noise of 1.3e- with the parallel multiple sampling and the two simultaneous output streams of 4Mpixel for a movie mode and 16Mpixel for a still mode with a 2.3Gb/s/lane high-speed interface. Moreover, the high speed output mode of 16Mpixel at 120fps with a low image degradation compression. The stacked structure realizes on an analog implementation of the double column parallel ADCs.

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This paper proposes 3D stacked module consisting of image sensor and digital logic dies connected through inductive coupling channels. Evaluation of a prototype module revealed radiation noise from the inductive coils to the image sensor is less than 0.4-LSB range along with ADC code, i.e., negligible. Aiming at high frame rate image sensor/processing module exploiting this attractive off-die interface, we also worked on resolving another throughput-limiter, namely power consuming Time to Digital Converter (TDC) used in column parallel ADCs. Novel intermittent TDC operation scheme presented in this paper can reduce its power dissipation 57% from conventional ones.

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In this paper, a 400^H × 256^V pixels 20 Mfps global shutter CMOS image sensor having 128 on-chip memories per pixel with improved sensitivity and power consumption performances is demonstrated. Due to the process technology development based on a 1P6M 0.18 μm CMOS image sensor process and the optimization of the signal readout circuitry with decreased supply voltage of 3.3 V, the fill factor, the conversion gain and the readout gain were all improved from the previous chip and an eight times higher light sensitivity and a 50 % decrease of power consumption were achieved simultaneously. The impact of the performance improvements was confirmed to be significant based on the captured movie video of UHS phenomena.

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We propose a practical method that realizes radiometric compensation based on direct and indirect light transports so that uncalibrated projector-camera systems can create desired image displays on 3D objects. By introducing compressed sensing, we efficiently construct the light transport matrix that includes direct/indirect light transports reflected from unknown 3D objects. Assuming that each camera pixel receives a linear summation of direct and indirect reflection lights via the color-mixing matrices, which are reformed by reference to the light transports, our proposed method adaptively compensates the color brightness output from the projector by controlling a feedback system. We demonstrate compensation trials that use reformed color-mixing matrices and confirm that our proposed method offers excellent projection-based displays on 3D objects.

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We propose a novel method for synthesizing a visible-light image from a near-infrared one taken from the same viewpoint. Generating a multi-channel color image from a single-channel one is generally an ill-posed problem. As texture and color cues, the method refers to visible-light color images of the same scene but taken from a different point. The proposed method focuses on the estimation of the luminance component rather than the chrominance one because chrominance is not sensitive for human vision, and relatively easier to be estimated than luminance. Our cost function to optimize the luminance component is designed with the assumption that the synthesized image should be globally similar to the input infrared image structure and locally similar to the reference image patterns. Our experimental results show that the proposed method produces an artificial visible-light image, whose color appearance is more natural than color conversion methods, and geometrically more accurate than texture transfer-based methods.

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OFDM (Orthogonal Frequency Division Multiplexing) modulation scheme is widely used in high speed communication systems. In OFDM system, one of the main problems is the influence of impulsive noise that has very large magnitude and short time duration. It causes significant degradation of the transmission performance. Therefore, an appropriate measure to reduce the influence of impulsive noise is required. In order to reduce the influence of the impulsive noise effectively, precise estimation of transmission channel is necessary. However, the pilot symbols for channel estimation are also affected by impulsive noise. We have already proposed the scheme for channel estimation under these situations using the pilot symbols inserted in two successive OFDM symbols. However, data transmission performance degrades because two successive OFDM symbols are inserted. In this paper, channel estimation scheme using only one OFDM symbol is proposed. As the result, possibility of precise channel estimation was confirmed.

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