Since recent scientific and engineering simulations require heavy computations with large volumes of data, High-performance Computing (HPC) systems need a high computational capability with a large memory capacity. Most recent HPC systems adopt a parallel processing architecture, where the computational capability of the processors is increasing, however, the performance of the memory system is constrained. The bytes per flop (B/F), which is a ratio of the memory bandwidth to the flop/s, for the HPC systems have been reduced with the evolution of the HPC systems. To fully exploit the potential of the recent HPC systems, and to meet the increasing demand for large memory, it is necessary to optimize practical scientific and engineering applications, considering not only the parallelism of the applications, but also the limitations of the memory subsystems of the HPC systems. In this paper, we discuss a set of approaches to optimization of the memory access behavior of the applications, which enable their executions with improved performance on the recent HPC systems. Our approaches include memory optimizations through memory footprint controlling, restructuring of data structures for active elements, redundant data structure elimination through combined calculations and optimized re-calculation of data. To validate the effectiveness of our approaches, a plasmonics simulation application is evaluated on vector platforms NEC SX-ACE, NEC SX-9, and Intel Xeon based platform NEC LX 406-Re2. By applying our approaches to the implementation, the memory usage of the plasmonics simulation application can be reduced up to nearly 1/71 of the original, and its execution can be possible on a single node of a distributed parallel system with smaller memory capacity. The optimization results in 1.14 times faster execution on SX-ACE and 1.81 times faster execution on LX 406-Re2.

Very low-density lipoprotein (VLDL) receptor is a member of the low-density lipoprotein (LDL) receptor family. It binds triglyceride rich lipoprotein (TGRL) but not LDL, because it recognizes apolipoprotein (apo)E only but not apoB. The VLDL receptor functions as a peripheral lipoprotein receptor in concert with lipoprotein lipase (LPL) in heart, muscle, adipose tissue and macrophages. In contrast to the LDL receptor, VLDL receptor binds apo E2/2 VLDL and apoE3/3 VLDL particles, and its expression is not down-regulated by intracellular lipoproteins. It has been reported that both LDL-cholesterol (LDL-C) and postprandial triglyceride (chyromicron and VLDL remnants) are risk factors for human atherosclerotic cardiovascular disease (ASCVD). True ligands such as lipoprotein particles of the VLDL receptor are chyromicron remnant (CMR) and VLDL remnant (postprandial hyperlipidemia). Although the oxidized LDL (oxLDL)-scavenger receptors pathway is considered to be the main mechanism for macrophage foam cell formation, it seems that the TGRL-LPL-VLDL receptor pathway is also involved. Since Lp(a) is one of the ligands for the VLDL receptor, the Lp(a)-VLDL receptor pathway is another potential alternative. The expression of VLDL receptor protein in mouse macrophages is modest compared to that in rabbit and human macrophages, both in vitro and in vivo. Therefore, we need to elucidate the mechanism of human ASCVD not by using the mouse model and scavenger receptors pathway but instead using the rabbit model and VLDL receptor pathway, respectively.

The main contribution of this paper is to present an implementation that performs the exhaustive search to verify the Collatz conjecture using a GPU. Consider the following operation on an arbitrary positive number: if the number is even, divide it by two, and if the number is odd, triple it and add one. The Collatz conjecture asserts that, starting from any positive number m, repeated iteration of the operations eventually produces the value 1. We have implemented it on NVIDIA GeForce GTX TITAN X and evaluated the performance. The experimental results show that, our GPU implementation can verify 1.31×10¹² 64-bit numbers per second. While the sequential CPU implementation on Intel Core i7-4790 can verify 5.25×10⁹ 64-bit numbers per second. Thus, our implementation on the GPU attains a speed-up factor of 249 over the sequential CPU implementation. Additionally, we accelerated the computation of counting the number of the above operations until a number reaches 1, called delay that is one of the mathematical interests for the Collatz conjecture by the GPU. Using a similar idea, we achieved a speed-up factor of 73.

Energy consumption has become a critical factor constraining the design of massively parallel computers, necessitating the development of new models and energy-efficient algorithms. The primary component of on-chip energy consumption is data movement, and the mesh computer is a natural model of this, explicitly taking distance into account. Unfortunately the dark silicon problem increasingly constrains the number of bits which can be moved simultaneously. For sorting, standard mesh algorithms minimize time and total data movement, and hence constraining the mesh to use only half its processors at any instant must double the time. It is anticipated that on-chip optics will be used to minimize the energy needed to move bits, but they have constraints on their layout. In an abstract model, we show that a pyramidal layout and a new power-aware algorithm allows one to sort with only a square root increase in time as the fraction of processors simultaneously powered decreases. Furthermore, this layout is shown to be optimal in terms of the time-power tradeoff required for sorting. Previous algorithms assumed fully powered systems, hence pyramid sorting was of no interest since when fully powered they are no faster than the base mesh. Our results show asymptotic theoretical limits of computation and energy usage on a model which takes physical constraints and developing interconnection technology into account.

Embedding graphs on the torus is a problem with both theoretical and practical importance. It is required to embed a graph on the torus for solving many application problems such as VLSI design, graph drawing and so on. Polynomial time and exponential time algorithms for embedding graphs on the torus are known. However, the polynomial time algorithms are very complex and their implementation has been a challenge for a long time. On the other hand, the implementations of some exponential time algorithms are known but they are not efficient for large graphs in practice. To develop an efficient practical tool for embedding graphs on the torus, we propose a new exponential time algorithm for embedding graphs on the torus. Compared with a well used previous exponential time algorithm, our algorithm has a better practical running time.

A Mobile Ad hoc Network (MANET) is a network that consists of mobile nodes and is autonomously managed without infrastructure base stations such as access points. MANETs have started being used as part of safety critical applications. A Vehicular Ad hoc Network (VANET) used in automated driving systems is such an example. In such applications, defects in the network protocol may cause serious social problems. Model checking, a state search-based verification technique, has proven to be effective in finding faults in complex system designs, such as communication protocols. However it is challenging to apply this technique to MANET protocols, because a MANET can have a number of different network topologies, thus resulting in the state explosion problem very easily. In this paper we propose a modeling technique to mitigate this problem using the AODV protocol as a running example. MANET protocols, such as AODV, typically enforce a source node that wishes to establish a route to the destination to retry the route establishing process some fixed number of times in face of failures. We show that to model check the protocol's behavior in these retries it suffices to consider only the last trial. The results of experiments using the SPIN model checker show that using the proposed technique significantly reduced the time and memory usage compared to standard full state exploration and allowed us to model check the protocol with up to five nodes.

概要. 本稿は，連立非線形方程式の新たな数値解法を提案する．目的は初期値に近い解を求めることである．これを実現させるために，代数方程式を解くアルゴリズムである平野法と，非線形最適化問題におけるArmijo法と似た考え方を用いる．各種の連立代数方程式や連立非線形方程式に対する数値実験により提案手法の有効性を検証した．