For cloud data center, Virtual Machine (VM) consolidation is an effective way to save energy and improve efficiency. However, inappropriate consolidation of VMs, especially aggressive consolidation, can lead to performance problems, and even more serious Service Level Agreement (SLA) violations. Therefore, it is very important to solve the tradeoff between reduction in energy use and reduction of SLA violation level. In this paper, we propose two Host State Detection algorithms and an improved VM placement algorithm based on our proposed Host State Binary Decision Tree Prediction model for SLA-aware and energy-efficient consolidation of VMs in cloud data centers. We propose two formulas of conditions for host state estimate, and our model uses them to build a Binary Decision Tree manually for host state detection. We extend Cloudsim simulator to evaluate our algorithms by using PlanetLab workload and random workload. The experimental results show that our proposed model can significantly reduce SLA violation rates while keeping energy cost efficient, it can reduce the metric of SLAV by at most 98.12% and the metric of Energy by at most 33.96% for real world workload.

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The low-pass filter (LPF) is a key component for high power RF generators generating 40.68MHz sine wave, since the LPF should reject harmonic noises and handle high input power simultaneously. We propose a novel LPF, operating at 30kW with good skirt performance. The proposed filter is a 7th order Butterworth type and consists of four capacitors and three inductors. The capacitors and inductors are implemented by copper plates, teflon insulators and copper plates with screws, respectively. The measured values of S₁₁, S₂₁ and phase of the proposed LPF are −26.4dB, −0.57dB, and −163.5 degrees at 40.68MHz, respectively. The S₂₁ values at 2nd (81.36MHz) and 3rd (122.04MHz) harmonics are −19.5dB and −29.3dB, respectively. The measured spectrum data on the surface of RF cable that is connected to the LPF output were −41.0dBm at 40.68MHz and −78.8dBm at 81.36MHz. The difference value of 37.8dB is sufficient for harmonic suppression. In addition, arcing and thermal problems do not occur.

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　本研究では，2050年に世界GHG排出量を1990年比半減する目標の実現可能性と，その社会経済影響を定量的に分析した．分析には応用一般均衡モデルを使用し，対象地域はアジアの主要10地域(中国，インド，インドネシア，日本，韓国，フィリピン，マレーシア，台湾，タイ，ベトナム)とした．
　結果から，国内削減のみを考慮した場合には日本と韓国を除いた8地域で排出量削減目標は技術的・経済的に達成可能である．日本・韓国においては国際的な排出量取引等の取り組みが目標達成に向けて必要不可欠である．また，目標達成に伴って経済的ロスが発生し，マレーシアを筆頭にタイ，インドネシア，ベトナム，中国にて10%以上のGDPロスが見られた．しかしながらこのロスを考慮してもGDPは現在と比較して増加し，経済発展は可能である．

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This paper presents a condition-monitoring method of dc-link capacitors used in a high-power three-phase PWM inverter with an evaluation circuit intended for ageing tests. Although its power rating is 1/25 of the inverter, the evaluation circuit provides the equivalent ripple current waveform and dc-bias voltage to the high-power inverter. The monitoring method independently extracts the capacitance and ESR of the dc-link capacitor, where the fast Fourier transform is introduced to the ripple current waveform and the dc-link voltage of the evaluation circuit. Experimental results verify that the monitoring method obtains both the ESR and capacitance changes of a capacitor under test.

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An FPGA plays an essential role in industrial products due to its fast, stable and flexible features. But the power consumption of FPGAs used in portable devices is one of critical issues. Top-down hierarchical design method is commonly used in both ASIC and FPGA design. But, in the case where plural modules are integrated in an FPGA and some of them might be in sleep-mode, current FPGA architecture cannot be fully effective. In this paper, coarse-grained power gating FPGA architecture is proposed where a whole area of an FPGA is partitioned into several regions and power supply is controlled for each region, so that modules in sleep mode can be effectively power-off. We also propose a region oriented FPGA placement algorithm fitted to this user's hierarchical design based on VPR[1]. Simulation results show that this proposed method could reduce power consumption of FPGA by 38% on average by setting unused modules or regions in sleep mode.

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Power consumption has become an increasing concern in high performance microprocessor design. Especially, Instruction Cache (I-Cache) contributes a large portion of the total power consumption in a microprocessor, since it is a complex unit and is accessed very frequently. Several studies on low-power design have been presented for the power-efficient cache design. However, these techniques usually suffer from the restrictions in the traditional Instruction Fetch Unit (IFU) architectures where the fetch address needs to be sent to I-Cache once it is available. Therefore, work to reduce the power consumption is limited after the address generation and before starting an access. In this paper, we present a new power-aware IFU architecture, named Analysis Before Starting an Access (ABSA), which aims at maximizing the power efficiency of the low-power designs by eliminating the restrictions on those low-power designs of the traditional IFU. To achieve this goal, ABSA reorganizes the IFU pipeline and carefully assigns tasks for each stages so that sufficient time and information can be provided for the low-power techniques to maximize the power efficiency before starting an access. The proposed design is fully scalable and its cost is low. Compared to a conventional IFU design, simulation results show that ABSA saves about 30.3% fetch power consumption, on average. I-Cache employed by ABSA reduces both static and dynamic power consumptions about 85.63% and 66.92%, respectively. Meanwhile the performance degradation is only about 0.97%.

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This paper proposes a new power decoupling method for a high-frequency cycloconverter which converts the single-phase line-frequency ac input to the high-frequency ac output directly. The cycloconverter consists of two half-bridge inverters, two input filter capacitors, and a series-resonant circuit. The proposed power decoupling method stores the input power ripple at double the line frequency in the filter capacitors. Therefore, the proposed method achieves a unity power factor in ac input and a constant current amplitude in the high-frequency output without any additional switching device or energy storage element. This paper theoretically discusses the principle and operating performance of the proposed power decoupling method, and the viability is confirmed by using an experimental isolated ac-to-dc converter based on the high-frequency cycloconverter. As a result, the proposed power decoupling method effectively improved the displacement power factor in the line current to more than 0.99 and reduced the output voltage ripple to 4% without any electrolytic capacitor.

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In recent years, conventional model-based motion control has become more challenging owing to the continuously increasing complexity of areas in which robots must operate and navigate. A promising approach for solving this issue is by employing interaction-based robotics, which includes behavior-based robotics, morphological computations, and soft robotics that generate control and computation functions based on interactions between the robot body and environment. These control strategies, which incorporate the diverse dynamics of the environment to generate control and computation functions, may alleviate the limitations imposed by the finite physical and computational resources of conventional robots. However, current interaction-based robots can only perform a limited number of actions compared with conventional robots. To increase the diversity of behaviors generated from body–environment interactions, a robotic body design methodology that can generate appropriate behaviors depending on the various situations and environmental stimuli that arise from them is necessitated. Electronics-free robotics is reviewed herein as a paradigm for designing robots with control and computing functions in each part of the body. In electronics-free robotics, instead of using electrical sensors or computers, a control system is constructed based on only mechanical or chemical reactions. Robotic bodies fabricated using this approach do not require bulky electrical wiring or peripheral circuits and can perform control and computational functions by obtaining energy from a central source. Therefore, by distributing these electronics-free controllers throughout the body, we hope to design autonomous and highly decentralized robotic bodies than can generate various behaviors in response to environmental stimuli. This new paradigm of designing and controlling robot bodies can enable realization of completely electronics-free robots as well as expand the range of conventional electronics-based robot designs.

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