One of the most challenging issues in wireless sensor networks is extension of the overall network lifetime. Data aggregation is one promising solution because it reduces the amount of network traffic by eliminating redundant data. In order to aggregate data, each sensor node must temporarily store received data, which requires a specific amount of memory. Most sensor nodes use (SRAM) or flash memory for storage. SRAM can be implemented in a one-chip sensor node at low cost; however, SRAM requires standby energy, which consumes a lot of power, especially because the sensor node spends most of its time sleeping, i.e. its radio circuits are quiescent. This study proposes two types of divided SRAM: equal-size divided SRAM and equal-ratio divided SRAM. Simulations show that both proposed SRAM types offer reduced power consumption in various situations.

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In order to analyze an impact of threshold voltage (Vth) fluctuation induced by random telegraph noise (RTN) on LSI circuit design, we measured a 40-nm 6-Tr-SRAM TEG which enables to evaluate individual bit-line current. RTN phenomenon was successfully measured and we also identified that the transfer MOSFET in an SRAM bit-cell was the most sensitive MOSFET. The proposed word line boosting technique, which applies slightly extra stress to the transfer MOSFET, improves about 30% of detecting probability of fail-bit cells caused by RTN.

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This paper describes a 0.13-\\micron CMOS made by using highly reliable copper and SiLK^T.M. (DOW CHEMICAL) interconnection technologies. We propose a hybrid interlayer structure with SiLK^T.M. at the trench level and SiO₂ at the via level to improve electrical properties, mechanical strength, and reliability. Using these technologies, we made a fully functional 1.5-Mbit SRAM macro and investigated the reliability of its copper wiring in terms of electromigration.

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In this paper, the balanced pre-charging and group decoding are presented to realize in-memory computing which can achieve continuous read operations after only one pre-charge operation. Compared with the analog computing of multi-row parallel reading, this structure adopts digital domain computing, which improves the accuracy of computing; compared with the non multi-row in-memory computing, it improves the computation speed. The simulation results of noise margin, read times, and read speed show that the proposed method can improve memory performance. The maximum stability can be improved by 13.8%, the read speed can be improved by 75%, and the power consumption can be reduced by 11.58%. Besides, it can be widely used in a variety of memory structures. The proposed method is applied to the existing in-memory computing structures to verify the effectiveness.

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An improved single event upset (SEU) tolerant

(SRAM) bit-cell with differential read and write capability is proposed. SPICE simulation suggests a more than 1000 times improvement of the critical charge over the standard 6T SRAM cell. With the SEU robustness greatly enhanced at low area and electrical performance costs, the proposed cell is well suited to harsh radiation environment applications such as aerospace and high energy physics.

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The self-improvement of (SRAM) cell stability by post-fabrication high-voltage stress is experimentally demonstrated and its mechanism is analyzed using 4k device-matrix-array (DMA) SRAM test element group (TEG). It is shown that the stability of unbalance cells is automatically improved by merely applying stress voltage to the V_DD terminal of SRAM. It is newly found that |V_TH| of the OFF-state pFETs in the SRAM cell is selectively lowered which improves the cell stability and contributes to the self-improvement.

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This paper presents an improved design of a radiation-hardened (SRAM). The simulation results based on the 0.18µm standard digital CMOS technology show that its static current drops dramatically compared with the WHIT cell, and the write speed is equivalent to that of other cells. The memory cell is extremely tolerant to logic upset as it does not flip even for a transient pulse with 100 times the critical charge of the ROCK cell. According to these features, this novel cell suits high reliability applications, such as aerospace and military.

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The susceptibility of a (SRAM) core against static and dynamic variation of power supply voltage is evaluated, by using on-chip diagnosis structures of memory built-in self testing (MBIST) and on-chip voltage waveform monitoring (OCM). The SRAM core of interest in this paper is a synthesizable version applicable to general systems-on-a-chip (SoC) design, and fabricated in a 90nm CMOS technology. RF power injection to power supply networks is quantified by OCM. The number of resultant erroneous bits as well as their distribution in the cell array is given by MBIST. The frequency-dependent sensitivity reflects the highly capacitive nature of densely integrated SRAM cells.

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This paper presents an improved design of a radiation-hardened (SRAM) cell. The memory cell is designed to be tolerant to transient single-event upsets by taking advantage of the fact that for the same area, the surface mobility of NMOS transistors is greater than that of PMOS transistors. The results show that the proposed design is able to withstand single-event upsets for temperatures between -55°C to 125°C when subjected to radiation intensities of 10¹⁴ rad(Si)/sec without affecting the write performance of the memory. The circuit is also robust when impinging high energy particle strikes at various angles of incidence.

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We propose a

based complementary metal-oxide semiconductor LSI chip that accelerates ground-state searches of an Ising model. Escaping local minima is a key feature in creating such a chip. We describe a method for escaping the local minima by asynchronously distributing random pulses. The random pulses are input from outside the chip and propagated through two asynchronous paths. In an experiment using a prototype of our chip, our method achieved the same solution accuracy as the conventional method. The solution accuracy is further improved by dividing the random pulse distribution paths and increasing the number of pseudo random number generators.

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In this paper, we present a novel six-transistor (6T) single-ended (SE-SRAM) cell for ultra-low-voltage applications. The proposed design has a strong 2.65X worst case read static noise margin (SNM) compared to a standard 6T SRAM. A strong write-ability of logic ‘one' is achieved, which is problematic in an SE-SRAM cell with a 36% improvement compared to standard 6T SRAMs. A 16 × 16 × 32 bit SRAM with proposed and standard 6T bitcells is simulated and evaluated for read SNM, write-ability and power. The dynamic and leakage power dissipation in the proposed 6T SRAM are reduced by 28% and 21%, respectively, as compared to standard 6T SRAM.

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This paper proposes a novel and an efficient method termed hypersphere sampling to estimate the circuit yield of low-failure probability with a large number of variable sources. Importance sampling using a mean-shift Gaussian mixture distribution as an alternative distribution is used for yield estimation. Further, the proposed method is used to determine the shift locations of the Gaussian distributions. This method involves the bisection of cones whose bases are part of the hyperspheres, in order to locate probabilistically important regions of failure; the determination of these regions accelerates the convergence speed of importance sampling. Clustering of the failure samples determines the required number of Gaussian distributions. Successful (SRAM) yield estimations of 6- to 24-dimensional problems are presented. The number of Monte Carlo trials has been reduced by 2-5 orders of magnitude as compared to conventional Monte Carlo simulation methods.

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This study proposes a novel one-write eight-read (1W8R) 20T multiport

- (SRAM) for codebook quantization in deep-learning processors. We manufactured the memory using a 40nm process and achieved a memory read-access time of 2.75ns and a power consumption of 2.7pJ/byte. Furthermore, we estimated the performance of an embedded super-multiport SRAM in the pipeline of a deep-learning processor. We employed NVDLA, NVIDIA's deep learning processor, as the motif and simulated it based on the power obtained from an actual proposed memory. We estimated the power consumption when inputting a 4,094× 2,048 (4K) image into the target model, which is a U-Net semantic segmentation model. The obtained power and area reduction results were 20.24% and 26.24%, respectively.

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In-Memory Computing (IMC) architectures based on

(SRAM) can improve system performance and energy-efficiency dramatically. However, most of the existing SRAM-based implementations are designed for specific purposes like accelerating neural networks, which limits the application scenarios of IMC. In this paper, we propose DM-IMCA, a novel IMC architecture with two work modes for general purpose processing. It utilizes our proposed 9T bitcell based computational SRAM as the location to perform IMC operations. Besides, a new IMC Instruction Set Architecture (ISA) as well as an automated vector computing mechanism are also proposed to facilitate DM-IMCA’s programming and accelerate in-memory computing, respectively. The simulation results show that DM-IMCA can bring a performance increase by up to 257x, and SRAM energy saving by up to 3x, compared to a baseline system.

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The (SRAM) is indispensable for high performance applications. With technology scaling, the device size as well as the operation supply voltage (VDD) is reduced. However, with the supply voltage decreasing, the performance of the conventional 6T SRAM is deteriorated seriously. In this letter, a symmetrical 10T SRAM with dramatically improved read stability and write ability is proposed. The simulation results indicate that, compared with the conventional 6T SRAM, the read static noise margin (RSNM) and write margin (WM) of the proposed 10T SRAM achieve 2.43× and 4.51× improvement, respectively, at a 0.8 V supply voltage in SMIC 65 nm technology. As a result, lower failure probability in access operations is expected. Moreover, the minimum supply voltage (VDD_min) of the proposed 10T SRAM achieves ∼0.32× compared with that of conventional 6T cell. Additionally, it also shows a better tolerance to the varying process variations.

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With advances in CMOS technology, the threshold voltage variation has worsened, which has a bad impact on the timing variation for sense amplifier enable signal. This paper proposes an oscillator replica bitline (ORB) technique for suppressing timing variation of SRAM sense amplifiers. The number of MOSFETs used in the ORB technology is approximately 40% of that in conventional replica bitline technique and the ORB technique can be programmed to modify sense amplifier enable timing. The simulation results show that, at a supply voltage of 0.8 V, the timing variation can be reduced by approximately 52.37% and 6.29% compared with the conventional replica bitline technique and replica bitline with multistage technique, respectively.

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In this paper, an improved SEU hardened SRAM bit-cell, based on the SEU physics mechanism and reasonable circuit-design, is proposed. The proposed SRAM cell can offer differential read operation for robust sensing. By using 90 nm standard digital CMOS technology, the simulation results show that the SRAM cell can provide full immunity for single node upset and multiple-node upset. And its critical charge is 25 times compared with Quatro10T. Besides, by comparing several electrical parameters, the proposed SRAM cell has the highly reliable and low-power capability for severe radiation environment application.

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