抄録
This paper designs a one-bit comparator and a one-bit half adder using complementary resistive switches (CRS) crossbar units. At first, the finite state machine (FSM) of the crossbar unit with two CRS cells is presented. Then, we demonstrate that the crossbar unit with a single CRS cell can realize the one-bit comparator in 7 sequential cycles, and the crossbar unit with two CRS cells which are connected via a wired AND (‘&’) can realize the one-bit half adder in 5 sequential cycles. Simulation results show that the one-bit comparator and the one-bit half adder can be designed to provide device area benefits via CRS crossbar units. The designs of one-bit comparator and one-bit half adder project the possibility of applications for complex circuit designs with CRS crossbar units.
