An LC-tuned sinusoidal voltage-controlled oscillator (VCO) using temperature-stable linear operational transconductance amplifiers (OTAs) is presented. Its architecture is based on Colpitts oscillator configuration, where the inductor is simulated one realized with four OTAs and a grounded capacitor. A prototype VCO built with discrete components exhibits less than 3% nonlinearity in its current-to-frequency transfer characteristic from 0.7-40MHz and 95ppm/°C temperature drift of oscillation frequency over 0 to 75°C. The total harmonic distortion (THD) is as low as 2.9% with a peak-to-peak amplitude of 0.7V for a specified frequency-tuning range. The phase noise of the VCO is about -105.2dBc/Hz at 1MHz offset frequency.

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A novel high power light-emitting diode lamp driving technology that uses a reverse charge pump circuit and digital dimming method instead of a conventional DC-DC converter is proposed to obtain a high circuit efficiency at all dimming levels. In this method, the voltages of all capacitors are kept constant by the period in which the capacitors are connected in parallel. From the experimental results, the circuit efficiency was kept constant irrespective of the dimming level and lighting condition. In addition, an average circuit efficiency of 91.8% was obtained when all of the light-emitting diode lamps were turned on at the same dimming level.

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A finite field multiplier is commonly used in implementations of cryptosystems and error correcting codes. In this paper, we present a low latency semi-systolic multiplier over GF(2^m). We propose a finite field multiplication algorithm to reduce latency based on parallel computation. The proposed multiplier saves at least 31% time complexity as compared to the corresponding existing structures.

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This paper designs a one-bit comparator and a one-bit half adder using complementary resistive switches (CRS) crossbar units. At first, the finite state machine (FSM) of the crossbar unit with two CRS cells is presented. Then, we demonstrate that the crossbar unit with a single CRS cell can realize the one-bit comparator in 7 sequential cycles, and the crossbar unit with two CRS cells which are connected via a wired AND (‘&’) can realize the one-bit half adder in 5 sequential cycles. Simulation results show that the one-bit comparator and the one-bit half adder can be designed to provide device area benefits via CRS crossbar units. The designs of one-bit comparator and one-bit half adder project the possibility of applications for complex circuit designs with CRS crossbar units.

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Color constancy algorithms are often used for illuminant compensation. This paper proposes an illuminant compensation method using a camera noise analysis without segmentation. Pixels within highlight regions generally include large amounts of information on the image illuminant. Thus, the analysis of highlight regions provides a relatively easy means of determining the characteristics of an image illuminant. Given that sensor non-uniformity affects illuminant estimation, the proposed method selects valid pixels within a highlight region by analyzing the chromatic noise characteristics of the camera. The illuminant is then estimated using a modified dichromatic reflectance model based on the selected valid pixels. Experimental results confirm that the proposed method is superior to other conventional methods.

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A compact quadrature coupler — using intertwined mutual inductors by the proposed GaAs integrated passive device (IPD) process — is developed by considering the quality factor of inductor and minimum insertion loss for the long term evolution (LTE) applications. At the center frequency of LTE bands 5 and 8, the quadrature coupler achieved −3.45dB of insertion loss S₂₁ and −3.43dB of coupling S₄₁ with less than 0.65 degrees of phase error over the frequency range. The reflection coefficient S₁₁ and the isolation S₃₁ are −24.32dB and −23.45dB, respectively. This coupler can be usable for a compact quadrature 3-dB divider/combiner as partial component of a balanced power amplifier.

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Estimating the precision of a multichannel telemetry data system accurately and efficiently is important because of the high cost of flight experiments and the complexity of telemetry data. System precision is significantly determined by the crosstalk effect. This paper proposes an efficient precision estimation method for data acquisition system based on multichannel phase-shift rectangular waveforms. The experiments are conducted to test the precision of the multichannel data acquisition system. Experimental results show that the proposed approach can estimate the precision of the acquisition system accurately; this finding was further validated by comparing the results with those of the IEEE Std 1057-2007 method. In addition, the measurement time of the proposed method was significantly shorter. In contrast to the existing method, the proposed method can locate faulty signal channels rapidly and estimate system precision effectively and efficiently.

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This paper proposes a design of voltage sensor with new controllable delay element (CDE) having high linearity and high resolution. The proposed CDE uses power supply node to measure the voltage value. However, the delay increases exponentially at low voltage level. In this paper we add a PMOS header in parallel with the conventional CDE to compensate the delay degradation at lower voltage. We develop a 16-levels fully digital voltage sensor with a voltage range of 0.8 ∼ 1.1V and 20mV resolution by using of the proposed delay elements. The proposed circuit is designed and simulated in a 45nm CMOS process. The simulation results show the feasibility of the high resolution and high linearity at low voltage by using of the proposed delay elements.

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A chip with which to manipulate microparticles using wireless power transfer and pulse-driven dielectrophoresis has been designed and fabricated using a 0.18-µm CMOS process. The chip enables microparticle manipulation using a 0.35-V power supply and a 10∼100kHz clock, which are generated on the chip by means of an on-chip coil, a rectifier and a ring oscillator circuit with process variation compensation circuits. The proposed process variation compensation with effective gate-width tuning as well as body biasing can achieve stable 0.35-V operation, allowing a 87% reduction in the power consumption of digital circuits on the chip compared to previous work.

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In this letter, design methodlogy of a low phase noise multiband film bulk acoustic resonator (FBAR) based voltage controlled oscillator (FBAR-VCO) is presented. It employs a 1.9GHz cross-coupled FBAR-VCO core, and extends oscillation to 0.65GHz, 0.98GHz, 1.96GHz and 3.92GHz by a divider and a multiplier. By analyzing the low frequency instability and proposing the solution based on a capacitor, cross-coupled architecture is employed in 1.9GHz FBAR-VCO core and phase noise degradation is extensively studied for extended frequencies. By considering the effect of transistors’ size on the Q-factor and impedance of FBAR, excellent phase noise and high loop gain are obtained. The post-layout simulation shows the proposed multiband FBAR-VCO achieves the lowest phase noise below −150dBc/Hz at 1MHz offset frequency.

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A fully integrated 3 ∼ 5GHz CMOS RF transceiver for IR-UWB applications is implemented in 0.18µm CMOS technology. The integrated RF notch filter is employed to reject the nearby WiFi and WCDMA interferers. The low power digital impulse generator is used as the UWB RF transmitter. The measured sensitivity of the receiver is −65dBm at 4GHz with 1Mbps PRF. And the measured energy efficiency per pulse is 20.6pJ/bit. The current consumption of the receiver and transmitter including DA is 27.5mA and 25.5mA, respectively, at 1.8V supply.

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