A novel delay optimization method for a critical path in VLSI design

Abstract

This paper presents a new method for optimizing the delay of a critical path with an embeded long wire for global routing. And an appropriate effective fan-out factor (EFOF) for optimizing the sizes of the devices in the critical path is derived. Simulations show that the new optimization method can obtain more accurate delay estimation for a critical path than traditional method, which offers significant result for automatic floor-plan and routing in VLSI design.