An improved quad Itoh-Tsujii algorithm for FPGAs

V. R. Venkatasubramani; N. Murali; S. Rajaram

doi:10.1587/elex.10.20130612

LETTER

An improved quad Itoh-Tsujii algorithm for FPGAs

V. R. Venkatasubramani, N. Murali, S. Rajaram

著者情報

キーワード: Field-programmable gate-array (FPGA)-based designs, quad Itoh-Tsujii algorithm (QITA), Lookup Table (LUT)

ジャーナルフリー

2013 年 10 巻 18 号 p. 20130612

DOI https://doi.org/10.1587/elex.10.20130612

Browse “Advance online publication” version

詳細

抄録

In this paper, we propose an improved quad Itoh-Tsujii algorithm to compute multiplicative inverse efficiently on Field-programmable gate-arrays (FPGA) platforms for binary fields generated by irreducible trinomials. Efficiency is obtained by eliminating the precomputation steps required in conventional quad-ITA (QITA) scheme. Experimental results show that the proposed architecture improves the performance on FPGAs compared to existing techniques.

責任著者(Corresponding author)

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