Abstract
Accurate analytical models for the strain and stress in silicon induced by annular Through-silicon-via (TSV) are proposed. Finite element method (FEM) is used for the model verification. It is shown that errors for the strain and stress models are respectively less than 6.6% and 6.8% for various metal and dielectric materials. Based on the analytical model of stress, keep-out-zones (KOZs) are also evaluated for pMOS and nMOS, as the stress is parallel and perpendicular to transistor channel. Annular TSVs with various materials induce KOZs of less than 6.6μm. W exhibits the best thermo-mechanical performance with KOZ=0.