IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
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A low-voltage CMOS MIN circuit with 3N+1 complexity and 10mV/10ns corner error
Jesús E. Molinar-SolísCarlos Muñiz-MonteroRodolfo Z. García-LozanoCuauhtemoc Hidalgo-CortesLuis A. Sánchez-GasparianoJosé M. Rocha-PérezAlejandro Díaz-SánchezJesús Efraín Gaxiola Sosa
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2013 Volume 10 Issue 22 Pages 20130755

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Abstract
An 1.5V CMOS voltage-mode MIN circuit with 3N+1 complexity and 10mV/10ns corner error is presented. The proposed approach uses a low impedance configuration to operate with low voltage supply requirements and without the need of low-voltage techniques with large area requirements. The basic cell and a LTA circuit prototype were simulated, fabricated and characterized using a double poly, three metal layers 0.5µm CMOS technology from ON SEMI foundry.
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© 2013 by The Institute of Electronics, Information and Communication Engineers
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