IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
Capacitance driven clock mesh synthesis to minimize skew and power dissipation
John ReubenMohammed Zackriya.VSalma NashitHarish M Kittur
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2013 Volume 10 Issue 24 Pages 20130850

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Abstract

Tree driven mesh is gaining popularity as a viable method to distribute clock with minimum skew in Deep Sub Micron (DSM) technology. In the design of the leaf level mesh, the density of the mesh at various parts of the chip is a crucial factor which decides the clock skew and power dissipated in the mesh. We propose a capacitance driven mesh formation methodology which forms a minimum wire length, non-uniform mesh when compared to the traditional skew-driven mesh. After connecting the sinks to the mesh by a combination of Steiner tree and stubs, appropriately sized buffers are placed at optimal locations such that skew and power dissipation are minimized. When our algorithms were tested on ISPD2010 benchmarks, the power dissipated in the mesh was found to be 25% lesser and the skew was 32% to 45% lesser than the skew driven mesh.

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© 2013 by The Institute of Electronics, Information and Communication Engineers
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