IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 10 , Issue 24
Showing 1-16 articles out of 16 articles from the selected issue
LETTER
  • Ehsan Kargaran, Yasser Mafinejad, Khalil Mafinezhad, Hooman Nabovati
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 24 Pages 20130264
    Published: December 25, 2013
    Released: December 25, 2013
    [Advance publication] Released: July 18, 2013
    JOURNALS FREE ACCESS
    In this paper, a new gain enhancement technique which is recommended for folded cascode LNA structures at low voltage and low power applications is presented. In order to increase power gain, a new modified version of gm-boosting technique is employed which increases the power gain while consuming no extra power. The new topology shares its DC current at the folded stage in order to reduce power dissipation associated with the gm-boosting technique. The proposed technique reduces power dissipation almost 27%, additionally; other parameters such as power gain and noise figure have been slightly improved. In the proposed LNA, power gain and noise figure are15dB and 3.2dB respectively. It consumes 1.3mW under 0.6 supply voltage.
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  • Seung-Won Yang, Jong-Yeol Lee
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 24 Pages 20130640
    Published: December 25, 2013
    Released: December 25, 2013
    [Advance publication] Released: December 09, 2013
    JOURNALS FREE ACCESS
    This paper presents a new low-power butterfly (BF) unit for single-path delay feedback FFT architectures exploited in multi-path FFT processors. In the proposed BF unit, the power consumption is reduced by replacing multiplexors connected to the outputs of adders in a conventional BF unit with AND gates at the inputs of the adders, which is possible by modifying BF operation. In bypass mode by using the AND gates to set an input of each adder to zero, we can reduce the switching activity in the adders and achieve additional reduction in power consumption. The proposed BF unit synthesized with a 0.13µm CMOS standard cell library achieves an average reduction of 24.8% in power consumption over the conventional BF unit.
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  • Zixuan Wang, Jianhui Wu, Qing Chen, Xincun Ji
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 24 Pages 20130729
    Published: December 25, 2013
    Released: December 25, 2013
    [Advance publication] Released: December 06, 2013
    JOURNALS FREE ACCESS
    A MASH 1-1-1 ΔΣ time-to-digital converter (TDC), based on two-stage time quantization, was designed with a 0.13μm CMOS process and a 1.2V supply. A classical delay line and a Vernier delay line were used for coarse and fine quantization, respectively. Third-order noise-shaping was achieved using the proposed MASH 1-1-1 ΔΣ modulator. Simulation results showed that a resolution of up to 5.5ps and a measurement range of 38.4ns could be achieved. The proposed TDC consumes 4.9mW and occupies 0.28mm2.
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  • Yasser Mafinejad, Majid Zarghami, Abbas Z. Kouzani, Khalil Mafinezhad
    Type: LETTER
    Subject area: Micro- or nano-electromechanical systems
    2013 Volume 10 Issue 24 Pages 20130746
    Published: December 25, 2013
    Released: December 25, 2013
    [Advance publication] Released: December 11, 2013
    JOURNALS FREE ACCESS
    This paper presents a wide band RF MEMS capacitive switch. The LC resonant frequency is reduced from mm wave to X band frequencies at down-state by using a meander type membrane, with the frequency band is being increased by adding two short high impedance lines at both ends of coplanar waveguide (CPW). Moreover, this acts as T-match circuit in up-state position and improves the matching. Simulation results demonstrate that the capacitance ratio reduces from 50 to 21.4, S21 and S11 are less than −10dB for the entire frequency band at down-state and up-state. Also, a comprehensive and complete electric model of the switch is proposed and simulation results agree well with the characteristics of the physical structure of the MEMS switch. Vpull-in and Vpull-out of this switch are 8.1V and 0.3V, respectively.
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  • Shun-ichiro Ohmi, Jun Arima
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2013 Volume 10 Issue 24 Pages 20130778
    Published: December 25, 2013
    Released: December 25, 2013
    [Advance publication] Released: December 09, 2013
    JOURNALS FREE ACCESS
    Contact resistivity reduction at PtSi/Si(100) interface by dopant segregation (DS) process was investigated by the cross-bridge Kelvin resistor (CBKR) method for the first time. After the 60 nm-thick PtSi was formed at 700oC/1min in N2 ambient, ion implantation (PH3 or BF3, 1×1015cm−2, 15 keV) was carried out followed by the drive-in anneal at 800oC/1min as a DS process. The Schottky barrier height (SBH) for electron and hole obtained from the C-V characteristics of PtSi/Si(100) diodes were 0.19eV and 0.23eV, respectively. The contact resistivity of 1.7×10−7Ωcm2 for PtSi/p+-Si(100) and 1.8×10−6Ωcm2 for n+-Si(100) were achieved even for the minimum contact area of 2.2μm2 and 33μm2, respectively.
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  • Donggu Im, lku Nam
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 24 Pages 20130789
    Published: December 25, 2013
    Released: December 25, 2013
    [Advance publication] Released: December 03, 2013
    JOURNALS FREE ACCESS
    A 0.1-5GHz ultra-wide band (UWB) single-to-differential (S-to-D) CMOS LNA with differential imbalance correction is implemented as a part of a software defined radio (SDR) which supports multi-band and multi-standard. The proposed S-to-D LNA is composed of a S-to-D converter, a differential-to-single (D-to-S) voltage summer with inductive shunt peaking, a negative feedback network, and a differential output buffer with composite common-drain (CD) and common-source (CS) amplifiers. By feeding the single-ended output of the voltage summer to the input of the LNA through a feedback network, a wideband S-to-D LNA exploiting negative feedback is implemented. By adopting common-drain based inductive shunt peaking, the S-to-D LNA achieves a wider gain bandwidth. A differential output buffer composed of two CS and two CD amplifiers corrects the imbalance of the differential output of the S-to-D converter. The 3dB gain bandwidth of the proposed S-to-D LNA is above 5GHz and the NF is below 4dB from 100MHz to 5GHz. An average power gain of 18dB and an IIP3 of −8 ∼ −2dBm are obtained. The differential output of the proposed S-to-D LNA has a gain difference of less than 0.3dB, and a phase imbalance of lower than 3° from 0.1GHz to 5GHz.
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  • Takanari Minami, Takashi Ohira
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2013 Volume 10 Issue 24 Pages 20130806
    Published: December 25, 2013
    Released: December 25, 2013
    [Advance publication] Released: November 21, 2013
    JOURNALS FREE ACCESS
    In this letter, we propose unified active Q factor formula for use in oscillator noise spectrum estimation from Leeson’s and Hajimiri’s models. This formula is derived from its oscillation condition as unified expression which covers the conventional formulas. Since this formula can reduce to conventional formulas, we confirm that the unified formula is valid regardless of topology and type of active device. In addition, we applied this unified formula to a cascode FET amplifier based oscillator as an example. As the result, we found that it has Q factor twice as high as a single FET oscillator using the same passive network. From these issues, we conclude that active Q factor can be estimated only if we know the oscillation condition and its frequency slope. It will contribute to low-phase-noise oscillator design and optimization.
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  • Hideki Fukano, Yohei Kushida, Shuji Taue
    Type: LETTER
    Subject area: Fiber optics, Microwave photonics, Optical interconnection, Photonic signal processing, Photonic integration and systems
    2013 Volume 10 Issue 24 Pages 20130812
    Published: December 25, 2013
    Released: December 25, 2013
    [Advance publication] Released: December 05, 2013
    JOURNALS FREE ACCESS
    We have developed a very simple high-sensitivity fiber temperature sensor using multimode interference. The fabricated multimode interference structure comprises a large-core multimode fiber (MMF) sandwiched between single-mode fibers. Silicone rubber is coated onto the MMF as a cladding material. This silicone rubber coating exhibits a large refractive-index change with temperature that produces a very fine temperature resolution as low as 1 × 10−2°C.
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  • Hari Kumar R, Balasubramani M, Ganesh Babu
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 24 Pages 20130848
    Published: December 25, 2013
    Released: December 25, 2013
    [Advance publication] Released: December 05, 2013
    JOURNALS FREE ACCESS
    This paper introduces an implementation of Wavelet Neural Network (WNN) with Particle Swarm Optimization (PSO) learning ability on Field Programmable Gate Array for detection of severity index of epileptic seizure detection. The Electroencephalography (EEG) signals were first pre-processed using discrete wavelet transforms (DWTs). This was followed by the feature selection stage, where five wavelet parameters and four representative summary statistics were computed. Four different activation functions were used in the hidden nodes of WNNs. The best combination to be used was the WNNs that employed Haar wavelet as the activation function, with Haar wavelet along with Heursure soft thresholding at the feature extraction stage. The PSO learning method is used in this paper. Twenty known epilepsy patients in nine defined groups are studied. The efficacy of the WNN is analyzed through sensitivity, specificity and classification accuracy. Higher the benchmark values will be the better classifier.
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  • John Reuben, Mohammed Zackriya.V, Salma Nashit, Harish M Kittur
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 24 Pages 20130850
    Published: December 25, 2013
    Released: December 25, 2013
    [Advance publication] Released: November 21, 2013
    JOURNALS FREE ACCESS
    Tree driven mesh is gaining popularity as a viable method to distribute clock with minimum skew in Deep Sub Micron (DSM) technology. In the design of the leaf level mesh, the density of the mesh at various parts of the chip is a crucial factor which decides the clock skew and power dissipated in the mesh. We propose a capacitance driven mesh formation methodology which forms a minimum wire length, non-uniform mesh when compared to the traditional skew-driven mesh. After connecting the sinks to the mesh by a combination of Steiner tree and stubs, appropriately sized buffers are placed at optimal locations such that skew and power dissipation are minimized. When our algorithms were tested on ISPD2010 benchmarks, the power dissipated in the mesh was found to be 25% lesser and the skew was 32% to 45% lesser than the skew driven mesh.
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  • Zheng Yang, Yani Li, Jingmin Wang, Zhangming Zhu, Yintang Yang
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 24 Pages 20130869
    Published: December 25, 2013
    Released: December 25, 2013
    [Advance publication] Released: December 09, 2013
    JOURNALS FREE ACCESS
    Based on SMIC 0.18μm standard CMOS technology, an input-powered vibrational energy harvesting interface circuit is proposed. It can be applied in energy harvesting devices for the extremely low voltage and high conversion rate. The simulation results show that the minimum input voltage could be as low as 0.15V by utilizing bulk-driven technique. Correspondingly, the voltage conversion efficiency can reach up to 80%. And the power conversion efficiency is also 80% when voltage equals to 0.25V. The proposed input-powered interface circuit, compared with the conventional output-powered circuits, can automatically shut down when the input voltage amplitude is low enough, thereby avoiding unnecessary energy loss.
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  • Bei Yu, Chixiao Chen, Fan Ye, Junyan Ren
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 24 Pages 20130882
    Published: December 25, 2013
    Released: December 25, 2013
    [Advance publication] Released: December 05, 2013
    JOURNALS FREE ACCESS
    Sample-time error between channels degrades resolution of time-interleaved analog-to-digital converters (TIADCs). A calibration method implemented in mixed circuits with low-complexity and fast-convergence is proposed in this paper. The algorithm for detecting sample-time error, which is widely applied to wide-sense stationary input signals, is based on correlation. The detected sample-time error is corrected by a voltage-controlled sampling switch. Experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise-and-distortion ratio improves 19.1dB, and the spurious-free dynamic range improves 34.6dB for a 70.12-MHz input after calibration. The convergence time of the calibration is about 20000 sampling intervals.
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  • Zhikuang Cai, Haobo Xu, Shixuan Que, Weiwei Shan, Jun Yang
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 24 Pages 20130887
    Published: December 25, 2013
    Released: December 25, 2013
    [Advance publication] Released: December 05, 2013
    JOURNALS FREE ACCESS
    An all-digital circuit for on-chip measuring the long-term jitter of Phase-Locked Loop (PLL) using the undersampling technique is presented in this paper. The circuit comprises the undersampling circuit, which samples the PLL output signal and the data analysis circuit, which calculates the statistical value of the jitter. The data statistics approach is based on accumulating data from multiple edge regions with cycle edge alignment, which is suitable for measuring the long-term jitter of PLL clock signal. The proposed built-in self-test (BIST) circuit can test the PLL output signal whose frequency is greater than 1GHz. And it can provide high measurement resolution that is up to 1ps. The circuit was designed in Verilog, and fabricated in TSMC 130nm CMOS process. Simulated results show the possibility of detecting 45ps RMS long-term jitter of a 1GHz clock with less than 2% error.
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  • Fengjuan Wang, Zhangming Zhu, Yintang Yang, Xiaoxian Liu, Ruixue Ding
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 24 Pages 20130894
    Published: December 25, 2013
    Released: December 25, 2013
    [Advance publication] Released: December 03, 2013
    JOURNALS FREE ACCESS
    Analytical model for thermal stress in silicon induced by coaxial Through-silicon-via (TSV) is proposed. ANSYS is employed to verify the proposed model. It is shown that the average errors are ∼2.5% for Cu and SiO2 filled coaxial TSV. Based on the analytical model, thermo-mechanical performance of coaxial TSV is studied. Design guide lines for coaxial TSV are also given: 1) the smaller the sizes of metal parts, especially the outer metal shell, the better the thermo-mechanical performance; and 2) the dielectric size and the TSV height play unimportant roles on the thermal stress state.
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  • Yuh-Shyan Hwang, Yi-Tsen Ku, Jiann-Jong Chen, San-Fu Wang
    Type: LETTER
    Subject area: Integrated circuits
    2013 Volume 10 Issue 24 Pages 20130922
    Published: December 25, 2013
    Released: December 25, 2013
    [Advance publication] Released: December 09, 2013
    JOURNALS FREE ACCESS
    A low-voltage second-generation current conveyor (CCII) and its oscillator application suitable for portable systems are proposed in the paper. The proposed current conveyor is based on an inverter-based low-voltage error amplifier and a current mirror. There are no on-chip capacitors in the proposed current conveyor, and it can be designed with standard CMOS digital processes and hence will reduce the cost of chip fabrication. Moreover, the architecture of the proposed circuit without cascoded MOSFET transistors is easily designed and suitable for low-voltage operation. The CCII could be operated in a very low supply voltage such as ±0.5V. The proposed CCII has been fabricated with TSMC 0.18μm CMOS process and applied to low-voltage CCII oscillator suitable for portable systems.
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