抄録
Signal integrity perturbations are unavoidable in current high performance circuits implemented in nanometer technologies. In this paper, a novel methodology based on the signal addition of two digital signals to verify skew violations is proposed. This methodology allows the implementation of a compact sensor for on-chip verification of the skew in digital interconnect signals. The monitor is implemented in a commercial CMOS 65 nm technology. The compact size of the monitor allows its use for verifying several internal nodes with low area penalty. The impact of process, power supply voltage and temperature variations (PVT) on monitor resolution is analyzed. Simulation results show that the monitor is effective for identifying abnormal skews due to signal integrity issues.
