IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Low complexity semi–systolic multiplication architecture over GF(2m)
Se-Hyu ChoiKeon-Jik Lee
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2014 Volume 11 Issue 20 Pages 20140713

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Abstract
This paper presents a semi-systolic Montgomery multiplier based on the redundant basis representation of the finite field elements. The proposed multiplier has less hardware and time complexities compared to related multipliers. We also propose a serial systolic Montgomery multiplier that can be applied well in space-limited hardware. Furthermore, a simple inversion based on the proposed scheme is presented.
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© 2014 by The Institute of Electronics, Information and Communication Engineers
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