2014 Volume 11 Issue 23 Pages 20140953
This letter presents a multi-rate clock and data recovery circuit realized in a standard 65-nm CMOS technology, which operates from 3.125 Gb/s to 22 Gb/s. In order to cover the wide frequency range, a modified four-stage differential ring VCO is exploited, which provides not only the fast tracking ability from its coarse tuning, but also the precise tra cking from its fine tuning. Also, a voltage-regulated active filter is employed to reduce the ripples of the VCO control voltages. It helps to fasten the lock-in time of the proposed CDR circuit and improve the jitter characteristics against PVT variations. Measurements reveal that the CDR chip demonstrates very wide capture range of 3.125 ∼ 22 Gb/s, 3.3 ps,rms data jitter at 20 Gb/s, and 112-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of 0.12 mm2 only.