抄録
This paper presents a multi-channel memory based architecture for parallel processing of large-scale graph traversal for field-programmable gate array (FPGA). By designing a multi-channel memory subsystem with two DRAM modules and two SRAM chips and developing an optimized pipelining structure for the processing elements, we achieve superior performance to that of a state-of-the-art highly optimized BFS implementations using the same type of FPGA.
