2015 Volume 12 Issue 14 Pages 20150448
Although HMM-based TTS has been studied for many years, there are some limitations such as real-time applications based on low-performance and low cost systems. In this paper, we present a design of a TTS co-processor used for HMM-based Text-to-Speech (TTS) hardware systems. Based on a dedicated FPU and resource sharing architecture, the co-processor can compute a lot of DSP algorithms required by HMM at very high speed. The system has been built and verified on the FPGA system with English and Vietnamese languages. The results show that it can compute up to 3 words per second at frequency of 100 MHz with the resources cost about 32,000 logic elements, 19,000 registers, and 957 KB memory.
