This letter investigates the effects of coaxial through-silicon via (TSV) on carrier motilities in the channels of nMOS and pMOS with channels along  and  orientations on (100) silicon. The keep-out zone (KOZ) induced by coaxial TSV and the effective area occupied by TSV and surrounding KOZ are evaluated. The results show that, the effective area is reduced by ∼92% by aligning the channels of pMOS along  orientation and nMOS along  orientation than the opposite orientations. The absolute error ranges from −12.5 µm to 7.2 µm as the anisotropic property of silicon are neglected.
Trong-Thuc Hoang, Hong-Kiet Su, Hieu-Binh Nguyen, Duc-Hung Le, Huu-Thu ...
Article type: LETTER
Subject area: Electron devices, circuits, and systems
2015 Volume 12 Issue 14 Pages
Published: 2015 Released on J-STAGE: July 25, 2015 Advance online publication: July 07, 2015
Although HMM-based TTS has been studied for many years, there are some limitations such as real-time applications based on low-performance and low cost systems. In this paper, we present a design of a TTS co-processor used for HMM-based Text-to-Speech (TTS) hardware systems. Based on a dedicated FPU and resource sharing architecture, the co-processor can compute a lot of DSP algorithms required by HMM at very high speed. The system has been built and verified on the FPGA system with English and Vietnamese languages. The results show that it can compute up to 3 words per second at frequency of 100 MHz with the resources cost about 32,000 logic elements, 19,000 registers, and 957 KB memory.
This paper presents a coplanar waveguide (CPW) method to extract the permittivity of dielectric materials. The extraction is implemented by specifying an estimated permittivity and then calibrating it repeatedly. The calibrating process lies on matching the simulated and measured propagation-constants, i.e., narrowing their difference until it is less than 1%. A single variable strategy is also proposed to accelerate the calibration. Compared with the transmission-line method, our method shows good agreement over a broad frequency range for silicon substrate, while it is easier to be implemented.
A low-power bus coding called Green Phase Difference Coding (GPD) is proposed to reduce the power consumption of long interconnects between multi-cores. In GPD, the Green-Modified coding (GM) is a novel low switching activity coding on the basis of Self-Corrected Green Coding (SGC). The mapping of GM coding between original set and converted set is modified to reduce bit transition. And the phase difference technology that uses the phase difference between the clock and data is introduced to replace decision bit. Based on SMIC 130 nm CMOS technology, the simulation results show that the GPD coding scheme achieves 37.51% and 4.13%∼8.29% energy reduction compared with the parallel bus by applying random data source and SPEC95/2000 CINT reference source, respectively.