抄録
In this express, we present a new architecture of digital phase interpolation (PI) controller with clock and data loops, which can greatly reduce the jitter of recovery clock by reducing the probability of the coarse phase jumping and interpolating among several fine phases. A demo design was implemented using 0.13 µm CMOS technology for verification, and the simulation results demonstrate that the recovered clock of the presented architecture has a peak to peak jitter no more than 29 ps under 2.5 Gbps received data, which shows no coarse phase dithering happening. The area of this proposed PI controller is only 0.1 mm2.
