IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
12 巻, 21 号
選択された号の論文の6件中1~6を表示しています
LETTER
  • Huihua Liu, Lei Li, Ping Li, Jun Zhang
    原稿種別: LETTER
    専門分野: Integrated circuits
    2015 年 12 巻 21 号 p. 20150617
    発行日: 2015年
    公開日: 2015/11/10
    [早期公開] 公開日: 2015/09/04
    ジャーナル フリー
    In this express, we present a new architecture of digital phase interpolation (PI) controller with clock and data loops, which can greatly reduce the jitter of recovery clock by reducing the probability of the coarse phase jumping and interpolating among several fine phases. A demo design was implemented using 0.13 µm CMOS technology for verification, and the simulation results demonstrate that the recovered clock of the presented architecture has a peak to peak jitter no more than 29 ps under 2.5 Gbps received data, which shows no coarse phase dithering happening. The area of this proposed PI controller is only 0.1 mm2.
  • Inseok Kong, Kyung-Sub Son, Kyongsu Lee, Jin-Ku Kang
    原稿種別: LETTER
    専門分野: Integrated circuits
    2015 年 12 巻 21 号 p. 20150752
    発行日: 2015年
    公開日: 2015/11/10
    [早期公開] 公開日: 2015/10/16
    ジャーナル フリー
    This paper presents a precise time-difference repetition technique to enhance the timing accuracy in repetition based time-to-digital converters (TDC). In the proposed scheme, any delay mismatches during timing difference repetition process can be removed. The proposed circuit could be used for multi-step TDC, delta-sigma TDC, and SAR-type TDC. The proposed scheme was designed and simulated with a 65-nm CMOS process. The proposed circuit shows a delay variation of about 100 fs in the presence of device mismatches, which is much less than that of conventional approaches. The input time range and the conversion rate is 480 ps and 100 Msps if applied to a 2-step TDC, respectively.
  • Myung Chul Park, Won Il Jang, Sang Gyun Kim, Hyuk Jun Oh, Yun Seong Eo
    原稿種別: LETTER
    専門分野: Integrated circuits
    2015 年 12 巻 21 号 p. 20150755
    発行日: 2015年
    公開日: 2015/11/10
    [早期公開] 公開日: 2015/10/16
    ジャーナル フリー
    An IR-UWB RF transceiver IC compliant with IEEE 802.15.6 WBAN is implemented in 0.18 µm CMOS technology. To achieve the low power and low complexity, the OOK receiver architecture using energy detection and the digitally synthesized transmitter are employed. For the rejection of the undesired interferers and DC offset, the RF active notch filter and the proposed DC offset reset switch are integrated and improve the sensitivity significantly. The measured sensitivity of the receiver is −87.5 dBm at 4 GHz with 1.579 Mbps. The power consumption of the receiver and transmitter are 57 mW and 0.4 nJ/bit respectively.
  • Wang Zhi-Ming, Zhao Zhuo-Bin, Liu Jun, Hu Zhi-Fu, Sun Xi-Guo, Cui Yu-X ...
    原稿種別: LETTER
    専門分野: Microwave and millimeter wave devices, circuits, and systems
    2015 年 12 巻 21 号 p. 20150760
    発行日: 2015年
    公開日: 2015/11/10
    [早期公開] 公開日: 2015/10/16
    ジャーナル フリー
    This paper presents the development of an 85–120 GHz high-gain and wide-band monolithic millimeter-wave integrated circuit (MMIC) amplifier using our own improved 70-nm InP pseudomorphic high electron mobility transistor (PHEMT) with ft = 247 GHz and fmax = 392 GHz. Edge-coupled line is used for DC blocking and radial subs are employed for RF bypass. Shunt RC networks and radial stubs are included in the bias circuitry to maintain amplifier stability. This amplifier is measured on-wafer with a small-signal peak gain of 14.4 dB at 92 GHz and greater than 11.5 dB from 85 to 120 GHz. The 3 dB bandwidth is above 35 GHz with a chip size of 1.6 × 1.1 mm2. To our knowledge, this MMIC amplifier has characteristics of much higher-gain per stage, wider-band and smaller chip size than others at the similar frequency band. The excellent results indicate that this MMIC amplifier has a great potential for pre-amplifier or interstage driving amplifiers applications at W-band or D-band.
  • Kee-Won Kim, Jun-Cheol Jeon
    原稿種別: LETTER
    専門分野: Integrated circuits
    2015 年 12 巻 21 号 p. 20150769
    発行日: 2015年
    公開日: 2015/11/10
    [早期公開] 公開日: 2015/10/22
    ジャーナル フリー
    In this study, we present an efficient finite field arithmetic architecture based on systolic array for multiplication which is a core algorithm for division and exponentiation operations. In order to obtain dedicated area-efficient circuits, we adopt Montgomery multiplication algorithm and systolic array. First of all we induce an efficient arithmetic algorithm from typical Montgomery multiplication using an effective factor, then we design an efficient semi-systolic array based multiplication architecture which is highly suitable for pipelined operations. The proposed multiplier saves at least 40% area complexity as compared to the corresponding existing structures.
  • Takuya Sakamoto, Shigeaki Okumura, Ryosuke Imanishi, Hirofumi Taki, To ...
    原稿種別: LETTER
    専門分野: Microwave and millimeter wave devices, circuits, and systems
    2015 年 12 巻 21 号 p. 20150786
    発行日: 2015年
    公開日: 2015/11/10
    [早期公開] 公開日: 2015/10/22
    ジャーナル フリー
    Measurement of heartbeats is essential in cardiovascular magnetic resonance imaging because the measurement must be synchronized with the phase of cardiac cycles. Many existing studies on radar-based heartbeat monitoring have focused on echoes from the torso only, and such monitoring cannot be applied to subjects in magnetic resonance scanners because only the head and soles can be seen from the outside. In this study, we demonstrate the feasibility of the remote monitoring of heartbeats from the subject’s soles using a 60-GHz ultra-wideband radar. The heartbeat intervals measured using the radar are quantitatively compared with those measured using conventional electrocardiography.
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