抄録
Zero switching point effect for successive-approximation-register (SAR) analog-to-digital converters (ADCs) is analyzed in this paper. Central span switching procedures are presented based on shifting zero switching points of digital-to-analog converter (DAC) to improve the linearity of SAR ADC and reduce DAC energy. Several central span switching procedures modified from previous merged-capacitor-switching (MCS) and monotonic switching schemes are analyzed, which is central span MCS (CS-MCS) and central span monotonic (CS-MON). By splitting most-significant-bit (MSB) capacitors, CS-MCS and CS-MON have linearity error reduction by a fact of 2 and √2. The DAC switching energy is reduced by 92.2% and 84.4% relative to conventional SAR ADC. With Vcm applied as reference voltage at LSB conversion, the energy reduction can be increased to 96.1% and 92.17%. Moreover, with comparator input transistors split into two parts, the energy reduction of CS-MCS switching procedure can be 95.3% and 97.6% with Vcm reference at LSB conversion. These central span switching procedures are not sensitive to Vcm accuracy since it is the reference only at least-significant-bit (LSB) conversions.
