Design optimization for capacitive-resistively driven on-chip global interconnect

Abstract

On-chip global wires are speed and power bottleneck in state-of-the-art chips. AC coupling technique is an efficient way to reduce interconnection delay and power. This paper proposes a new capacitive-resistively driven AC coupling global link. Bandwidth performance of the proposed wire is analyzed and an optimization algorithm for capacitive-resistively driven wire is presented. Simulation results show that our optimization methodology can improve the bandwidth. By applying our optimization algorithm, data rate can be improved from 2 Gb/s to 2.5 Gb/s in the implemented transceiver circuit. The proposed optimization algorithm can be applied in high speed global communication.