IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
An ultra-high-speed FPGA based digital correlation processor
Meteb M. AltafEball H. AhmadWei LiHouxiang ZhangGuoyuan LiChangshun Yuan
Author information
Keywords: FPGA, FFT, correlation
JOURNAL FREE ACCESS

2015 Volume 12 Issue 8 Pages 20150214

Details
Abstract

This paper presents an ultra-high-speed correlation processor for FPGA (Field-Programmable Gate Array) which is based on MDF (multiple-path delay feedback) pipelined FFT (fast Fourier transform) architecture. In order to decrease the resource cost and processing delay, the FFT processor is based on DIF (Decimation in Frequency) decomposition method, and the IFFT processor is based on DIT (Decimation in Time) decomposition method. The data input and output of the correlation processor are both in natural order. The main clock speed of the processor FPGA implementation can be higher than 200 MHz and is able to process continuous complex input at more than 1.6 Gsps (giga samples per second).

Content from these authors
© 2015 by The Institute of Electronics, Information and Communication Engineers
Previous article Next article
feedback
Top