抄録
A boosted replica cell voltage control scheme has been proposed for reducing the process-variation of SRAM sense amplifier. This technique suppresses the timing variation by boosting the replica cell voltage. Simulation result shows that the variation of the generated timing was 34.6% smaller when compared with conventional technique, and the cycle time is reduced by 17% at a 0.85 V VDD operation in TSMC 65 nm technology with this scheme.
