IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration
Xiaoyun LiHoupeng ChenQian WangXi LiYu LeiQi ZhangXi FanJiajun HuZhen TianZhitang Song
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2017 Volume 14 Issue 2 Pages 20160901

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Abstract

An enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration was presented. Four transistors were added in this design to transfer bias voltages or ESD voltages. This circuit was simulated in 0.18 µm silicon-on-insulator (SOI) CMOS process and 28 nm HKMG CMOS technology. Spectre-simulation results showed that the ESD discharge current is increased by 2 times and the discharge current is decreased to nA magnitudes compared to the conventional circuit.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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