2017 Volume 14 Issue 2 Pages 20160901
An enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration was presented. Four transistors were added in this design to transfer bias voltages or ESD voltages. This circuit was simulated in 0.18 µm silicon-on-insulator (SOI) CMOS process and 28 nm HKMG CMOS technology. Spectre-simulation results showed that the ESD discharge current is increased by 2 times and the discharge current is decreased to nA magnitudes compared to the conventional circuit.