A 3.2-to-4.6 GHz fast-settling all-digital PLL with feed forward frequency presetting

抄録

This paper presents a 3.2-to-4.6 GHz fast-settling all digital fractional-N phase-locked loop (ADPLL) for multimode multiband receivers. Firstly, in this ADPLL, the wideband digitally controlled oscillator (DCO) is designed with a constant frequency step in the Coarse Mode to ensure constant loop bandwidth in the whole frequency range. Secondly, a feed-forward presetting path between frequency command word (FCW) and oscillator tuning word in the Coarse Mode (OTW^C) is utilized to accelerate the locking process for large frequency hopping steps. Thirdly, an adaptive locked and unlocked controller (ALUC) is used to allow frequency mode (Coarse/Medium/Fine Mode) to shift automatically. Implemented in a 65 nm CMOS process, the ADPLL on-chip part consumes 16 mW at 1 V voltage supply. The phase noise at 3.982 GHz is −121.8 dBc/Hz@1 MHz. The ADPLL with a final bandwidth of 65 kHz exhibits 55 µs transient settling time for a 1.232 GHz frequency hopping.