IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis
Meng LiuZhiwei ZhangWenqin SunDonglin Wang
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JOURNALS FREE ACCESS

2017 Volume 14 Issue 20 Pages 20170935

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Abstract

Clock tree design plays a critical role in improving chip performance and affecting power. In this paper, we propose a novel symmetrical clock tree synthesis algorithm, including tree architecture planning, matching, merging, embedding and buffer insertion. Obstacle-aware placement and routing are also integrated into the algorithm flow. By using NGSPICE simulation for benchmark circuits, our skew results decrease by 17.2% while using less than 24.5% capacitance resource compared with traditional symmetrical clock tree. Further, we also validated the algorithm in ASIC design.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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