An improved timing error prediction monitor for wide adaptive frequency scaling

抄録

In order to eliminate the excess timing margin in integrated circuit due to PVT variations, we propose a low overhead timing error prediction monitor, which has only 14 transistors with negligible power overhead. It can generate a predicted alarm signal when the timing is intense before real errors occur. A bunch of timing monitors are inserted at the end of selected critical paths. When there are timing prediction signals, the system clock will be stretched immediately to avoid real timing errors. Applied on a computation intensive Bitcoin Miner chip under 40 nm CMOS process, the simulation results show that it can operate at a wide voltage range of 0.5–1.1 V. This timing prediction monitor based adaptive frequency scaling system can increase the frequency to 2.1× at near-Vth voltage and 1.21× at super-Vth region compared to the original non-monitored circuit. Thus, it is an effective way to mitigate the effect of PVT variations.