A 2 GS/s 14-bit current-steering DAC in 65 nm CMOS technology for wireless transmitter

Abstract

A 14-bit 2 GS/s current-steering digital-to-analog converter (DAC) for transmitter application has been fabricated in TSMC 65 nm CMOS technology. To obtain high linearity, the DAC is segmented as 5+9, where the 5-MSB bits are implemented in unary architecture and 9-LSB bits are implemented in binary architecture. The current source array utilizes the random switching scheme to suppress the graded error and symmetrical error caused by process or thermal gradient. In addition, the DAC’s dynamic performance is enhanced by adopting a digital pre-distortion algorithm and measurement results validate the proposed technique. The measured spurious free dynamic range (SFDR) before and after enabling pre-distortion scheme improves from 63.8 dBc to 70.0 dBc at 240 MHz output signal. Dual-tone and four-tone measurement results show that the DAC achieves the 3^rd order intermodulation (IM3) lower than −64 dBc. The DAC occupies an active area of 0.19 mm² and consumes a total power of 490 mW from 1.3 V and 2.0 V supplies.