2018 Volume 15 Issue 2 Pages 20171202
This paper presents a practical, low-overhead, one-cycle correction better-than-worst-case design method for ultra-low voltage digital circuits. Excessive design margin for PVT variation brought by traditional worst-case design method is eliminated. Proposed method is completely compatible with EDA tools. Considerable design efforts are relaxed compared with other variation-tolerant techniques. We have implemented our proposed technique on a 16 bits × 16 bits pipelined multiplier in SIMC 55 nm CMOS process. The experimental results show that our proposed technique can get about 59% energy efficiency improvements compared with operating in worst-case timing margin.