A robust, subthreshold 12T SRAM bitcell with BL leakage compensation and bit-interleaving capability

抄録

This paper presents a novel 12T SRAM bitcell suitable for subthreshold operation. To make bit-interleaving structure feasible and eliminate half-select disturbance, the proposed cell features single pass-gate and dual pass-gates for read and write operation respectively. Additionally, the access path is decoupled by dedicate transistors from the true storage node, which both enhances the read stability and ensures enough sensing margin. Multi-threshold voltage metric is utilized to improve writability and leakage consumption. Simulation results show that the proposed cell offers 1.8X read static noise margin (RSNM) and 1.6X negative write static noise margin (WSNM) compared with traditional 6T cell at 0.4 V, sensing margin and access performance are improved compared with 10T cell.