Study on scalability of hybrid junctionless FinFET and multi-stacked nanowire FET by TCAD simulation

抄録

This work studied the electrical characteristics of silicon-on-insulator (SOI) multi-stacked nanowire junctionless FET (NW-JL-FET) and SOI hybrid junctionless FinFET (H-JL-FET) using TCAD simulation. The scalability of the above two structures was investigated by simulating device performance with gate lengths from 30 nm to 5 nm. Results show that NW-JL-FET has better performance than that of H-JL-FET due to gate all around structure. However, H-JL-FET still has good performance under ultra-small gate length indicating FinFET still could be a competitor for 5 nm and beyond technique nodes.