Two CMOS time to digital converters using successive approximation register logic

Abstract

This letter presents two CMOS time-to-digital converters (TDCs) with a conventional successive approximation register (SAR) logic and SAR continuous disassembly (CD) logic. In a flash TDC, a high-bit thermometer to binary converter consumes a large silicon area and power, which prevents the simple flash TDC structure be widely used in modern electrical devices. By separating the delay chain in a flash TDC with binary sequences, the SAR logics can eliminate the thermometer to binary code converter essential for a flash TDC. The two TDCs using conventional SAR and SAR CD logics were fabricated in a 0.18 µm CMOS technology with power consumption of 1.5 mW and 1.3 mW at a sampling rate of 10 Msamples/s and occupied 0.074 mm² and 0.041 mm² active areas, respectively.