This letter presents two CMOS time-to-digital converters (TDCs) with a conventional successive approximation register (SAR) logic and SAR continuous disassembly (CD) logic. In a flash TDC, a high-bit thermometer to binary converter consumes a large silicon area and power, which prevents the simple flash TDC structure be widely used in modern electrical devices. By separating the delay chain in a flash TDC with binary sequences, the SAR logics can eliminate the thermometer to binary code converter essential for a flash TDC. The two TDCs using conventional SAR and SAR CD logics were fabricated in a 0.18 µm CMOS technology with power consumption of 1.5 mW and 1.3 mW at a sampling rate of 10 Msamples/s and occupied 0.074 mm2 and 0.041 mm2 active areas, respectively.
A quadrature voltage-controlled-oscillator (QVCO) is presented and fabricated in standard 0.18 µm RF CMOS technology. Passively Capacitor coupling, actively bottom-series (BS) coupling and splitting switching biasing (SSB) techniques are combined and employed for the QVCO to improve its phase noise performance without loss of the voltage headroom. Measured results show the proposed QVCO achieves a tuning range from 0.88 to 1.04 GHz, phase noise of −71.2 dBc/Hz@1 kHz and −113.1 dBc/Hz@1 MHz, and a phase-noise figure-of-merit (FOMT) of 189.7 dBc/Hz from a offset frequency of 1 kHz, with an occupied die area of 1283 µm × 715 µm and power consumption of 11 mW from a 1.8 V voltage supply.
An integrated low frequency ratio wideband filtering duplex slot antenna with high isolation is proposed in this letter. The antenna consists of two layers: four circular slots are sequentially introduced between two layers, four orthogonal slotlines are etched to connect them, which are used as radiation structures; two pairs of split-ring resonators (SRRs) are inserted into two orthogonal microstrip line baluns ending in open stubs on both top and bottom layers, respectively, which is considered as the feeding network. Then, two independent broad operation bands are achieved by employing two orthogonal broadband resonator-based filtering feeding lines to excite circular slot mode. Furthermore, both filtering characteristic and polarization diversity help to improve port isolation, which contributes to frequency duplex function. The antenna is fabricated and tested. The measured results indicate that the impedance bandwidths of the lower-and-upper-band channels are 24.5% (2.29–2.93 GHz) and 17.5% (3.11–3.71 GHz), respectively. Low frequency ratio (1.05) is achieved. Port isolation is better than 42 dB and the cross polarization level is below 26 dB.
Along with the scaling up for network-on-chips (NoC), the network traffic grows increasingly, and generally the central region is easily to become the traffic hotspots. The problem of unbalanced traffic can lead to a part of network links becoming the bottleneck of network communication, and thus hurt the network and system performance. In this paper, we propose load-balanced link distribution method, which is intended to allocating physical channels according to the traffic load on each link. To support connecting multiple physical channels between two routers, we propose a novel concept of virtual port, and design a low-cost multi-port router called virtual port router (VP-Router). Compared to the network with traditional routers, the network with VP-Routers can effectively balance the network traffic load on links. The experiments with SPLASH2 benchmarks exhibit that VP-Router performs 6.3% and 9.0% better in energy-delay-product (EDP) for 4 × 4 and 8 × 8 mesh networks respectively. As for system throughput, VP-Router improves by about 3.5% and 5.8% on average respectively.
A linear and exponential (sqrt2 rule) combined curve fitting (CF) is proposed for low-energy shared cache partitioning. Considering cache’s inherent characteristics between cache miss rate and its size, function with an exponent of (1-sqrt2) fits the region of non-linear high-utility cache size, while linear function fits both regions of linear high-utility and low-utility cache size. Using the fitted functions, we proposed a scheme with purely mathematical formulization of energy consumption, which helps fast and efficient shared cache partition. Experimental results show that CF based shared cache partitioning scheme achieves up to 34.5% energy savings compared with other traditional techniques. Moreover, our approach has a high prediction accuracy for the shared cache miss rate and the energy.
A Ku-band receiver chain for phased array system is presented in this paper. It is composed of three LNAs, a 4-bit attenuator and a 5-bit phase shifter. This design is fabricated in 180-nm standard CMOS with a chip area of 3 mm × 0.8 mm. The measured peak gain is 21 dB at 16.5 GHz and the minimum NF is 6.7 dB at 16 GHz. The 5-bit phase shifter realizes a shift range of 0–360°. The tested minimum RMS phase error and gain error of the system are 2.1° and 0.46 dB. The 4-bit attenuator provides a gain tuning range of 15 dB with 1-dB step. The minimum RMS phase shift error and amplitude error are 2.7° and 0.24 dB.
An all-digitally phase-locked loop (ADPLL) with a pipeline time-to-digital converter (TDC) is proposed in this paper. The TDC employs a programmable-gain time amplifier (PGTA) to achieve two-step time quantization. A compensator is used to correct the gain error of the PGTA. The low-voltage DCO uses current-reuse structure to achieve lower and use bridging-capacitance technique to achieve high frequency resolution. The proposed design is validated by the ADPLL fabricated in the 65-nm CMOS technology. The measurement results show that the in-band and out-band phase noises are −90 dBc/Hz@10 kHz offset and −130 dBc/Hz@1 MHz offset, respectively. The RMS and peak-peak jitter are 1.24 ps and 8.65 ps respectively.
Read retry is one of the most effective methods to reduce retention errors caused by charge loss. A novel valley search algorithm for fast read retry method is proposed in this paper, which can reduce read operations to two times from at least three by conventional valley search algorithm [1, 8]. Experimental results illustrate that raw bit error rate (RBER) after read retry is reduced to 0.0344% using the novel valley search algorithm, which is within 4.41% of BCH(9088,8192,64) error correcting code (ECC) [2, 3] error correction capability.
An innovative extendible wireless power transfer system with load independent output voltage is developed in this paper. This system eliminates the interference caused by the cross coupling between nonadjacent coils and unrelated circuit networks among the receiving coils. The wireless power transfer system consists of a full-bridge converter power supply, transmitting resonator, relay resonators, and multiple receiving resonators. The theory of load independent output voltage is demonstrated in detail in this paper. The structure and features of the system has also been carefully illustrated. The simulation and experimental results show that the multiple receiving resonators do not affect each other when obtaining power and that the system can obtain load-independent output voltage. Experimental results and simulation analysis are highly consistent and the integrity of the theory is verified.
In this letter, a balanced sub-harmonic mixer based on a dual-mode ring coupler is proposed for EHF satellite communications. Theoretical analysis is given to show that the proposed balanced sub-harmonic mixer has the ability to suppress the odd harmonics of LO and its mixed products. It can improve the poor spurious suppression performance commonly encountered with traditional sub-harmonic mixer. A balanced sub-harmonic mixer based on the proposed structure is designed and fabricated. Measurement results show the mixer achieves good performance in terms of conversion loss and spurious suppression.
A wideband multiple input multiple output (MIMO) antenna with enhanced isolation for wireless communication application is presented in this article. The proposed antenna operates in a wide frequency range of 1.92–6.1 GHz, and is suitable for WiMAX, IEEE 802.11a/b/n/g, UMTS, LTE-2300 and LTE-2500 wireless communications. The MIMO antenna structure of the proposed antenna consists of two identical radiators with a small size of 35 × 36 mm2 and a novel H-shaped parasitic element, which is connected to the ground plane of the proposed antenna. The H-shaped parasitic element helps in enhancing antenna isolation performance between the two antenna ports. The overall performance of the proposed antenna in terms of S-parameters, radiation pattern, gain, and envelope correlation coefficient is investigated and verified through the measurements. The measured results show that the proposed antenna has attractive properties such as compact size, the low mutual coupling of less than −15.4 dB, and a low envelope correlation coefficient of less than 0.14 across the whole operating frequency band. These attractive properties make the proposed antenna a good candidate for wireless communication application.
A novel high PSRR and inherent temperature compensated CMOS voltage reference is present. A resistorless self-biased current source (RLSBCS) is proposed, formed by a gate-source voltage division (GSVD) structure, to achieve a temperature compensated proportional threshold-voltage difference. Meanwhile, a self-cascode structure is adopted to further cancel the residual negative temperature dependence of proposed threshold-voltage difference. Besides, feedback and self-bias techniques are introduced to enhance PSRR. The temperature coefficient is 4.9 ppm/°C in the temperature range of −25°C to 75°C and PSRR at DC is −82 dB with a power consumption of 9.8 nW.