Capacitance multiplier with large multiplication factor, high accuracy, and low power and silicon area for floating applications

抄録

A capacitance multiplier with high accuracy and reduced power consumption and silicon area, is presented. It offers a scaling factor based on ratios of resistors that can be physically matched to reduce deviations due to fabrication process. Resistor ratios also offer the property to define large scaling factors without increasing power consumption or silicon area. It is based on a modified current-mode multiplication technique that scales voltage magnitude instead of internal devices of the current-providing device. Simulation results show scaling factors of 10, 100, 1 k and 10 k. Experimental testing shows the results of the implementation of the floating equivalent multiplier implemented in a notch RLC filter with a scaling factor of 1 k.