An ultra-low-power 2.4 GHz RF receiver in CMOS 55 nm process

Abstract

This paper presents a 2.4 GHz ISM-band wireless receiver suitable for ultra-low-power (ULP) operation. In this design, a sliding-IF receiver architecture is adopted for achieving desired noise performance with low power consumption. Moreover, a new circuit design method is proposed for achieving ULP design. Some low power circuit techniques such as inverter based amplifier, current reuse and sub-threshold biasing techniques are presented in the design. The proposed receiver is designed and fabricated in a standard 55 nm CMOS process. The measurement results show a voltage gain of 29.2 dB, a noise figure (NF) of 6 dB and third-order intercept point (IIP3) better than −20 dBm. The receiver consumes 2.4 mW from a 1.2-V supply. The core area of the receiver is 0.5 mm².