Design of a power efficient self-adaptive LVDS driver

Abstract

A self-adaptive technique is presented for a low voltage differential signaling (LVDS) driver. By combining a high speed voltage detection circuit and drive capability control loop, the proposed architecture can adapt to the changes of output load and operating frequency automatically. This makes the driver suitable for using in field programmable gate array (FPGA), where load and frequency variation is large. Compared to previously reported LVDS drivers with fixed drive capability, the proposed driver eliminates power wasting under small load and low frequency condition. A prototype chip has been fabricated in 130 nm CMOS technology. Test results show the proposed driver improves maximum bit rate to 2.2 Gb/s and reduces power consumption by 48% compared to previously reported works with fixed drive capability.