An energy-efficient parallel VLSI architecture for SVM classification

抄録

This letter presents an energy-efficient VLSI architecture for SVM classification. Instead of accurate calculation, cost-reduced computing elements based on approximative techniques are designed to complete computation-intensive operations in the SVM-based classifier to save energy and resources. Besides, a partial parallel structure is applied to eliminate dimensional constraints for inputs of classifiers and balance between classification speed and energy consumption. We adopt 55-nm CMOS process to implement the proposed design. It occupies 0.0901 mm² area and consumes 15.9 mW at operating frequency of 100 MHz and from an operating voltage of 1 V. Experiment shows that the design provides an area reduction by 41.5% and a significant saving in energy efficiency by 61.8% compared with the baseline model.