Reliable packaging of Josephson voltage standard circuit for cryocooler operation

Abstract

Reliable and easy fabricated packaging for a Josephson voltage standard circuit was proposed and the thermal stress and temperature distribution in the chip were numerically analyzed. The chip for programmable Josephson voltage standard circuits was bonded with InSn solder to a copper plate to achieve good thermal contact. Although this packaging allowed very good thermal contact, the chip sometimes broke due to thermal stress caused by a difference in the expansion coefficient between silicon and copper. Slits were thus added to the copper plate to reduce the thermal stress. The numerical analysis suggested that the slits reduce the thermal stress in the voltage standard chip, and thus reduce the risk of the chip cracking when it is cooled. The numerical analysis also suggested that the temperature increase in the chip was about 1 mK which caused a negligible reduction in the operating margin of the PJVS operation.