A new three-dimensional (3-D) frequency selective surface (FSS) based on rectangular waveguide cavities is presented, which realizes a quasi-elliptic bandpass response by multiple transmission zeros/poles. Each unit cell of the proposed FSS is composed of an empty rectangular waveguide cavity and a cuboid circuit board with two back-to-back square loops. With the help of the rectangular waveguide cavities, the electrical and magnetic coupling paths are constructed, resulting in two transmission poles. The constructed out-of-phase signal paths cause two transmission zeros in the upper stopband. To explain the operating principle of the proposed FSS, an equivalent circuit model is given and analyzed using the odd- and even-mode method. A prototype of the proposed FSS is fabricated and measured. The measured results agree well with the simulated results, and show that the FSS can achieve a stable response to variations of incident angle from 0° to 60° for both TE and TM polarizations with wide out-of-band rejection. In addition, the proposed design also realizes a relatively small unit cell.
There are two major challenges in developing the sensing circuit for ReRAM in deep submicron technologies, including: 1) the reduced sensing margin (SM) due to the lowered supply voltage (VDD). 2) the degraded read access pass yield caused by the increased process-voltage-temperature (PVT) variations. A Reference Clamping Sense Amplifier (RC-CSA) with Amplifier Assisted load PMOS and Dynamic Pre-charge circuit is proposed to deal with these two challenges. Simulation results show that the RC-CSA is able to provide over 200 mV SM with VDD down to 0.55 V, and capable to work with a large bit-line loading (4096 cells per BL). The typical read yield is 99.9% for 32-Mb macro with sensing time of 4.6 ns under 0.75 V VDD. Overall, RC-CSA is very suitable for low-VDD and high-density applications.
Reliable and easy fabricated packaging for a Josephson voltage standard circuit was proposed and the thermal stress and temperature distribution in the chip were numerically analyzed. The chip for programmable Josephson voltage standard circuits was bonded with InSn solder to a copper plate to achieve good thermal contact. Although this packaging allowed very good thermal contact, the chip sometimes broke due to thermal stress caused by a difference in the expansion coefficient between silicon and copper. Slits were thus added to the copper plate to reduce the thermal stress. The numerical analysis suggested that the slits reduce the thermal stress in the voltage standard chip, and thus reduce the risk of the chip cracking when it is cooled. The numerical analysis also suggested that the temperature increase in the chip was about 1 mK which caused a negligible reduction in the operating margin of the PJVS operation.
Beacon systems for Internet of Things (IoT) services require frequent battery replacement and costly maintenance. To resolve these issues, we developed a novel beacon system. This system does not require Power over Ethernet (PoE) to supply power because it uses Ethernet energy-harvesting technology via the RJ45 port of the router and switching hub. We experimentally confirmed that the power produced through the Internet TCP/IP network signals activated the beacon dongle to transmit signals, and that a smartphone then received these signals.
Due to the high input current harmonics created from the power diodes as well as the switching of the inverter, the power factor cannot achieve a unity power factor. This paper presents an improved active power factor correction (APFC) converter for three-phase asynchronous motor drive system. This improved APFC operating in a discontinuous inductor current mode based on bridgeless canonical switching cell is designed and corrects the power factor in grid. In order to obtain high performance of the motor drive system, the dual-mode control strategy and the fuzzy PID is used in this system. Finally, the whole system is verified by software simulation and hardware experiment.
STT-MRAM has been considered to be one of the most promising non-volatile memory candidates due its non-volatility, high speed, and unlimited endurance etc. However, with technology scaling down, STT-MRAM suffers from high sensitivity to process voltage and temperature (PVT) variations. Additionally, the negative bias temperature instability (NBTI) effect has become an important factor affecting the life of the pMOSFETs used in an STT-MRAM sense amplifier. Therefore, designing a more reliable sense amplifier has become a critical challenge. In this paper, a novel architecture for a sense amplifier is proposed, which includes switching transistors to decrease the NBTI effect on the pMOS device, and a balanced transistor to decrease the sensitivity of the sense amplifier to process variations.
In this paper, we propose a simplified weighted least square (SWLS) to estimate phase variations utilizing pilots, for Orthogonal Frequency Division Multiplexing (OFDM) based very high throughput wireless local area networks (WLANs). For SWLS, the common phase error (CPE) maximum likelihood (ML) estimation and the angle boundary treatment are improved to enhance the performance of phase estimation, while the combined scheme of pair pilots is used to reduce the complexity. Simulation results show that, compared to weighted least square (WLS) scheme, a similar pocket error rate (PER) is achieved by using the SWLS method, but more than 40 percent of complexity is reduced.
This paper proposes a broadband Class EF power amplifier based on a low-pass filter matching structure. Based on the theory of Class EF power amplifiers, the optimal fundamental load impedance required is derived. A broadband matching circuit is then designed using a low-pass filter prototype. In the meantime, a compact harmonic control circuit is proposed to meet the harmonic impedance requirements of class EF power amplifiers. In order to validate the effectiveness of the proposed method, a 2.6–3.6 GHz broadband class EF power amplifier is designed and fabricated. Measurement results show that the output power is between 40.68 dBm and 41.6 dBm at 1 dB compression point in 2.6–3.6 GHz. From 62% to 78% drain efficiency is obtained with gain greater than 10 dB.
In this paper, we develop an efficient parallel semi-systolic array structure to concurrently compute multiplication and squaring operations in the binary extension field, GF(2m), for efficient modular exponentiations. The proposed array is well suited to VLSI implementation that it has a regular structure as well as local communications between its processing elements. The obtained results show that the proposed array structure achieves a significant reduction in area-time (AT) complexity by at least 95.9% over the corresponding existing structures.
A proof-of-concept delta sigma AD modulator using dynamic analog components with simplified operation mode is designed and fabricated in 90 nm CMOS technology. The measurement results of the experimental prototype demonstrate the feasibility of the proposed modulator architecture which can guarantee the reset time for ring-amplifier and relax the speed requirement on the asynchronous SAR quantizer. The peak SNDR of 77.93 dB and SNR of 84.16 dB are achieved while a sinusoid −4 dBFS input is sampled at 14 MS/s with signal bandwidth of 109 kHz. The total analog power consumption of the prototype modulator is 720 µW under the supply voltage of 1.2 V.
Voltage scaling is an effective technique for ultra-low-power applications. However, PVT variation degrades the robust of traditional synchronous pipelines severely when voltage scales into the sub-threshold region. In this paper, we propose a register-based bundled-data asynchronous pipeline that can operate robustly in sub-threshold, called Snake. By looping the match delay line, the Snake halves the design overhead compared to other asynchronous pipelines. We also propose a practical asynchronous design methodology which is compatible with commercial EDA and needs only a few modifications to synchronous design flow. Monte-Carlo SPICE simulation shows that the pipelined multiplier applying the proposed techniques operates stably in 0.2 V and achieves minimum power 1.3 nW in 0.2 V, minimum energy 1.07 pJ per cycle in 0.3 V. It provides 6.7 times superiority over synchronous baseline design with 22% area overhead. Comparison with other works in the state of art shows the proposed techniques are quite competitive.