Upset and damage mechanisms of the three-dimensional silicon device induced by high power microwave interference

Abstract

The paper clearly reveals the mechanism of upset (bit error) and damage caused by high power microwave (HPM) interference for the three-dimensional silicon device. The 0.35 µm process related three-dimensional model of two stages cascaded CMOS inverters is established for the first time utilizing semiconductor device simulator Sentaurus-TCAD to comprehendingly study the HPM interference mechanism. Moreover, a detailed mechanism about the upset induced by HPM interference is performed. Furthermore, the process and mechanism of damage generated by HPM interference are explored by using this model. The dependences of the damage power threshold P and damage energy threshold E on the pulse-width τ are both in negative exponential relationship. The simulation results in this paper have a good coincidence with the experimental results.