This paper presents a low-voltage 3rd-order single-bit switched-capacitor Σ-Δ modulator implemented in a 40-nm CMOS technology. In the modulator, a 2-tap FIR (finite impulse response) filter is employed in the feedback loop to reduce the integrator output swings. With the help of digital assisted techniques, the number of the sampling capacitors in the first integrator is reduced to mitigate the performance deterioration caused by capacitor mismatch. Besides, the inverter-based amplifiers with dynamic-biased structure are proposed to reduce the power consumption. The proposed modulator is sampled at 25.6 MHz over a bandwidth of 100 kHz. The modulator achieves a max SNR (signal-to-noise ratio) of 92.1 dB, a max SNDR (signal-to-noise and distortion ratio) of 87.3 dB, and a DR (dynamic range) of 88.1 dB under the supply voltage of ±0.45 V while consuming a total power consumption of 790 µW.
This paper introduces a method to improve the spatial resolution of the point light source detection in scintillator by offering a scintillation detector with a new structure. By introducing a lightproof material with multiple pinholes between the scintillator cube and photon sensors, the light source can be detected through photon reverse ray tracing method. The proposed scintillation detector can provide fine spatial resolution about 10 µm∼20 µm, which is more than 10× finer than the prior arts. To optimize the design, the impact of the design parameters on the detection resolution is discussed based on the detailed simulation results. The simulation result shows that with the optimized parameter choice we can further improve the spatial resolution to 5 µm∼10 µm.
Low power and thermal design techniques are more advantageous for high-performance memory cells. Body bias is an adaptive technique used for power and thermal management in memory systems. It offers an efficient solution for the memory’s power and thermal problems. In this study, a thermal management controller is presented as a complete hardware tuning loop. The controller is applied on both Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) units that actively monitors and controls the temperature via the power dissipation control in both memory types. The proposed combined circuits within the tuning loop are able to reduce the high power and temperatures, and dragging it around safe limits to avoid chip hardware damages. Results confirm that, the power dissipation of 6T SRAM cell is reduced by 9.77%, while the power of 1T1C DRAM cell is reduced by 8.50%. Thermal reduction was in the range of (5°C–10°C) per each body bias step voltage.
A RC-LIGBT with separated LDMOS and LIGBT by the L-shaped SiO2 layer is proposed and investigated. The L-shaped SiO2 layer enhances the bulk electric field remarkably and decreases the surface electric field substantially in the breakdown state. At the forward conduction, the current is dominated by the unipolar mode (LDMOS) before point A and bipolar mode (LIGBT) after point B, the snapback is eliminated between point A and B due to the conductivity modulation is restricted at the LIGBT region. The Free-Wheeling diode (FWD) is realized by the LDMOS region at reverse conduction state. Compared with the conventional RC-LIGBT, the proposed device shows snapback-free property and it increases the BV by 107% at the same time.
A novel approach is proposed for the design of broadband and high-efficiency power amplifier (PA), with elliptic low-pass and band-pass filtering matching networks in this letter. Based on the equivalent circuit model of the GaN HEMT, the optimal topology of output matching network (MN) is designed as elliptic low-pass matching network with two attenuation poles, and the input MN is designed as band-pass matching network in the distributed form. A series of design procedure of the proposed topology is presented in detail. In this design, a 10-W GaN HEMT device (CGH40010F) was used. Results of measurement show that a broadband high-efficiency PA is realized from 1.45 to 2.55 GHz (fractional bandwidth = 55%) with measured drain efficiency of 70%–84% and output power of 40.4–42.4 dBm.
ELCB (Earth leakage circuit-breaker) is a circuit breaker used in a low-voltage AC (Alternating Current) electrical circuit to provide electric shock protection and to prevent fires from current leakages. Trip operating time of ELCB depends on the magnitude of leakage current and the duration time of leakage accident. In this paper, the circuit and electrical signal after ZCT (Zero-sequence Current Transformer) output terminal of existing ELCBs are analyzed. As a result of measurement, electronic trip type ELCBs in present market have shown up to 27 ms of self-trip operating time under 30 mA of leakage current. This 27 ms of time delay is due to the problem that the IC in electronic circuit detects only the reverse-half cycle of sinusoidal leakage current. In this paper, the authors design a new electronic circuit that minimizes the delay factors of existing circuits. And as a result of an experiment, the trip operating time could be shortened within 9 ms. Shortened trip operating time implies reduction of shock duration of leakage current. Since the electric shock to human body and the outbreak possibility of fire are inversely proportional to square root of shock duration, faster trip operation of ELCB proposed in this paper will contribute to providing shock protection to human body and preventing fires from current leakages.
A dual-mode dielectric resonator antenna (DRA) and array fed by planar slot are presented. The bandwidth is expanded by merging the adjacent bands corresponding to TEy1δ1 and TEy1δ3 modes. The measured results are in good agreement with the simulated ones. The measured −10 dB bandwidth is 17.8% and the average gain is 6.5 dBi. Furthermore, a 2 × 2 DRA array is developed, which is improved with 45.5% impedance bandwidth and a peak gain of 12.6 dBi. The proposed dual-mode dielectric resonator antenna structure is promising for high-frequency applications due to its merits of simple feeding structure and wide band.
In this paper, A variable substrate integrated waveguide (SIW) phase shifter is presented. The phase shifter is formed by capacitively coupling varactors to a longitudinal slot on a SIW. Compared to other SIW phase shifters, our design is tunable, and only occupies 7.5 mm longitudinal length. Experiment results indicate the device is shown to have up to 60 degrees phase shift in the 5.3–6 GHz range with insertion loss better than 3 dB and return loss generally better than 20 dB.
The paper clearly reveals the mechanism of upset (bit error) and damage caused by high power microwave (HPM) interference for the three-dimensional silicon device. The 0.35 µm process related three-dimensional model of two stages cascaded CMOS inverters is established for the first time utilizing semiconductor device simulator Sentaurus-TCAD to comprehendingly study the HPM interference mechanism. Moreover, a detailed mechanism about the upset induced by HPM interference is performed. Furthermore, the process and mechanism of damage generated by HPM interference are explored by using this model. The dependences of the damage power threshold P and damage energy threshold E on the pulse-width τ are both in negative exponential relationship. The simulation results in this paper have a good coincidence with the experimental results.
A compact and low-power wireless receiver supporting 2.4 GHz industrial, scientific and medical (ISM) band is implemented in a 130 nm Complementary Metal–Oxide–Semiconductor (CMOS) process. The GHz operating frequency renders the chip to be matched with a mm-sized antenna to reduce implants’ size and improve patients’ experience. To simplify the implanted chip, the downlink is through On-Off Keying (OOK) so non-coherent detection and simplified receiver chain can be deployed. Boosted Rectifier and open-loop amplifier-based receiver chain lowers the chip’s power consumption to nW level. The measured sensitivity reaches −50 dBm at a Bit Error Rate (BER) of 1e-3.
This Letter presents a 0.8–3.4 GHz process variation insensitive full-swing duty-cycle corrector (DCC) for high-speed memory I/O links. The proposed DCC utilizes a new full-swing duty cycle adjuster (DCA) that can provide a full-swing output clock of 50% duty-cycle without using a small-swing to full-swing level shifter. The proposed full-swing DCA is based on a new pseudo-differential feedback delay element (PFDE) and fundamentally eliminates the problem of increased duty-cycle errors due to the use of a level shifter that is vulnerable to process corner variation. The proposed DCC is implemented in a 40-nm CMOS process and achieves an operating frequency range of 0.8–3.4 GHz. The duty-cycle correction range is ±15% at 3.4 GHz. The DCC dissipates 2.8 mW from a 1.0 V supply at 3.4 GHz and occupies an active area of only 0.0054 mm2.
An ultra-low leakage energy efficient level shifter that can convert extremely low input voltage into the supply voltage level is presented in this paper. In order to reduce the leakage power dissipation, the super-cut-off mechanism and MTCMOS technique are utilized in the proposed structure. At the same time, a positive feedback circuit is inserted to avoid the loss of performance. Post-layout simulation results in a 55-nm MTCMOS process demonstrate that for the voltage level conversion from 0.3 V to 1.2 V, the proposed level shifter exhibits a propagation delay of 70.77 ns and an energy per transition of 89.55 fJ for input frequency of 1 MHz. Meanwhile, the static power of the proposed level shifter is as low as 27.82 pW. The proposed level shifter only occupies 7.79 um2, which demonstrates prominent area efficiency.
This paper presents a DC offset calibration (DCOC) method combined with analog and digital circuits for direct conversion receivers. To work effectively, the LNA is shut off for better isolation and replaced by an equivalent resistance to keep the same transfer function of DC offset between calibration and operation. This method adopts DACs to compensate DC offset, then averages and eliminates the residual DC offset in the digital domain. Measurements show that this DCOC method achieves 0.44 mV DC offset and improves IM2 by 10 dB. The DCOC circuits occupy 0.23 mm2 in 40 nm CMOS and consume 124 µA at 1.3 V supply.
This paper presents an all-digital calibration technique for time-interleaved ADC (TIADC) timing mismatch. The calibration architecture is based on a channel multiplexing architecture. For a M-channel TIADC, only one centralized calibration module is needed. Timing mismatches between channels are estimated by correlating the adjacent channel’s outputs and a compensation algorithm based on the one-order five-point differentiator is employed to suppress the mismatches. Compared with conventional parallel calibration architecture, the proposed calibration architecture works well in higher Nyquist bands (NB) with high-scalability. The hardware consumption does not increase linearly with the number of sub-ADCs.
This letter reports a novel quasi-elliptic bandpass filter (BPF) using a new triple-mode circle-shaped substrate integrated waveguide (SIW) cavity. The triple-mode SIW cavity is achieved by a dual-mode circle-shaped SIW cavity with a floating capacitive-loaded metallic patch. The resonance of one higher-order mode is independently shifted to that of dual modes to form a three-pole passband. Three finite transmission zeros (FTZs) can be produced, and two of them can be controlled well by the angle between two feeding lines. For the demonstration, a prototype filter was designed, fabricated and measured. Good agreement between measured results and simulated results is observed. The proposed triple-mode SIW filter has the merits of compact size, high selectivity and controllable bandwidth as well as FTZs.
This paper demonstrates the design flow of a quick-start pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool. The quick-start PWPLL converts the internal state into an analog-digital mixed signal called soft-thermometer-code (STC) and stores them into memory before PWPLL is turned off in order to enhance the start-up in the next turn-on. Our chip fabricated with TSMC 65 nm shows 220 ns settling time (13 reference clock cycles), 858 µW power consumption under 1 V nominal supply voltage with 59 µm × 58 µm silicon area. The measurement results demonstrate that the design-automated PLL realizes the FoM of −221.7 dB, which is roughly the same value as that of the manually-designed one with the same target specification.