Five-stage pipelined dual-edge deblocking filter architecture for H.265 video codec

Abstract

High-Efficiency Video Coding (HEVC/H.265) is the latest video coding standard used in various applications. In HEVC, the quality of the reconstructed video is enhanced by two in-loop filters (Deblocking filter and Sample Adaptive Offset filter). In this paper, we propose an efficient resource sharing hardware architecture for deblocking filter. This architecture utilizes four edge filters to filter two edges of the 8 × 8 block in parallel. The edges are filtered following the sequential filter ordering. The proposed architecture is implemented in Verilog HDL and synthesized using Synopsys DC. The simulation results show that this architecture can process a 16 × 16 block in 45 clock cycles and hence an LCU in 720 clock cycles. It utilizes an area of 93.5 K in 32 nm technology supporting UHD video which is suitable for real-time applications.